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Commit eed3f139 authored by Jayant Shekhar's avatar Jayant Shekhar
Browse files

msm: mdss: Add core clock level selection in MDSS 



Currently core clock is calculated for each frame and
depending upon the calculated value clock driver rounds it
to the nearest clock level from clock table. Now do
quantization of required clock rate at mdp driver itself
once before the request goes to clock driver.

Change-Id: Ie30947fb8f7d2978bb121b28920c05888332bf3f
Signed-off-by: default avatarJayant Shekhar <jshekhar@codeaurora.org>
parent 281d1f8a

Documentation/devicetree/bindings/fb/mdss-mdp.txt

+9 −0
Original line number Diff line number Diff line
@@ -301,6 +301,12 @@ Optional properties: 
				used to reduce the pending writes limit dynamically

				and can be tuned to match performance requirements

				depending upon system state.

- qcom,mdss-clk-levels:		This array indicates the mdp core clock level selection

				array. Core clock is calculated for each frame and

				hence depending upon calculated value, clock rate

				will be rounded up to the next level according to

				this table. Order of entries need to be ordered in

				ascending order.



Fudge Factors:			Fudge factors are used to boost demand for

				resources like bus bandswidth, clk rate etc. to
@@ -406,6 +412,9 @@ Example: 
		qcom,mdss-ib-factor = <3 2>;		/* 1.5 times  */

		qcom,mdss-clk-factor = <5 4>;		/* 1.25 times */



		/* Clock levels */

		qcom,mdss-clk-levels = <92310000, 177780000, 200000000>;



		qcom,max-bandwidth-low-kbps = <2300000>;

		qcom,max-bandwidth-high-kbps = <3000000>;

drivers/video/msm/mdss/mdss.h

+3 −0
Original line number Diff line number Diff line
@@ -155,6 +155,9 @@ struct mdss_data_type { 
	struct mdss_fudge_factor ib_factor_overlap;

	struct mdss_fudge_factor clk_factor;



	u32 *clock_levels;

	u32 nclk_lvl;



	struct mdss_hw_settings *hw_settings;



	struct mdss_mdp_pipe *vig_pipes;

drivers/video/msm/mdss/mdss_mdp.c

+17 −0
Original line number Diff line number Diff line
@@ -2385,6 +2385,23 @@ static int mdss_mdp_parse_dt_misc(struct platform_device *pdev) 
	if (rc)

		pr_debug("max bandwidth (per pipe) property not specified\n");



	mdata->nclk_lvl = mdss_mdp_parse_dt_prop_len(pdev,

					"qcom,mdss-clk-levels");



	if (mdata->nclk_lvl) {

		mdata->clock_levels = kzalloc(sizeof(u32) * mdata->nclk_lvl,

							GFP_KERNEL);

		if (!mdata->clock_levels) {

			pr_err("no mem assigned for mdata clock_levels\n");

			return -ENOMEM;

		}



		rc = mdss_mdp_parse_dt_handler(pdev, "qcom,mdss-clk-levels",

			mdata->clock_levels, mdata->nclk_lvl);

		if (rc)

			pr_debug("clock levels not found\n");

	}



	return 0;

}

drivers/video/msm/mdss/mdss_mdp_ctl.c

+25 −0
Original line number Diff line number Diff line
@@ -988,6 +988,29 @@ exit: 
	mutex_unlock(&mdss_mdp_ctl_lock);

}



static int mdss_mdp_select_clk_lvl(struct mdss_mdp_ctl *ctl,

			u32 clk_rate)

{

	int i;

	struct mdss_data_type *mdata;



	if (!ctl)

		return -ENODEV;



	mdata = ctl->mdata;



	for (i = 0; i < mdata->nclk_lvl; i++) {

		if (clk_rate > mdata->clock_levels[i]) {

			continue;

		} else {

			clk_rate = mdata->clock_levels[i];

			break;

		}

	}



	return clk_rate;

}



static void mdss_mdp_ctl_perf_update(struct mdss_mdp_ctl *ctl,

		int params_changed)

{
@@ -1055,6 +1078,8 @@ static void mdss_mdp_ctl_perf_update(struct mdss_mdp_ctl *ctl, 
				clk_rate = max(ctl->cur_perf.mdp_clk_rate,

					       clk_rate);

		}



		clk_rate  = mdss_mdp_select_clk_lvl(ctl, clk_rate);

		mdss_mdp_set_clk_rate(clk_rate);

		pr_debug("update clk rate = %d HZ\n", clk_rate);

	}