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Commit ee862b80 authored by Sarangdhar Joshi's avatar Sarangdhar Joshi
Browse files

ARM: dts: msm: add coresight etm components for msmzirc 



Add device tree entries for CoreSight ETM components which are necessary to
enable processor trace.

Change-Id: If1ab911b7faecedd3bd01080f976aeabe90a7882
Signed-off-by: default avatarSarangdhar Joshi <spjoshi@codeaurora.org>
parent 2ae03f66

arch/arm/boot/dts/qcom/msmzirc-coresight.dtsi

+39 −0
Original line number Diff line number Diff line
@@ -100,6 +100,45 @@ 
		clock-names = "core_clk", "core_a_clk";

	};



	etm0: etm@842000 {

		compatible = "arm,coresight-etm";

		reg = <0x842000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <6>;

		coresight-name = "coresight-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <4>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	rpm_etm0 {

		compatible = "qcom,coresight-rpm-etm";



		coresight-id = <7>;

		coresight-name = "coresight-rpm-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <0>;

	};



	modem_etm0 {

		compatible = "qcom,coresight-modem-etm";



		coresight-id = <8>;

		coresight-name = "coresight-modem-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <2>;

	};



	csr: csr@801000 {

		compatible = "qcom,coresight-csr";

		reg = <0x801000 0x1000>;