usb: phy-msm-usb: Add support for Femto PHY

Synopsys 28nm Femto PHY is connected to the Chipidea USB2.0 link
on Ferrum target. The following changes are made to support the
Femto PHY.

- A new PHY type called SNPS_FEMTO_PHY is added to make the Femto PHY
specific changes. The targets that use this PHY should pass
qcom,hsusb-otg-phy-type = 2 from the device tree.

- PHY CSR IO memory is available that provides register level
interface for accessing the PHY. This register interface is used
for putting PHY in retention, HV interrupts management. It is
also possible to override the PHY parameters via this interface.
But the parameter overriding through this new interface is not
implemented in this patch.

- New reset clocks phy_reset_clk and phy_por_clk are introduced
to reset the whole PHY block (PHY CSR, ULPI bridge, Femto PHY)
and only the Femto PHY (POR signal).

- A new clock phy_csr_clk is required to access PHY CSR registers
via AHB2PHY interface. This clock is turned off during low power
mode.

- The USB link register USB_PHY_CONTROL interface is not available
on the Femto PHY. Add wrappers for HV interrupts and retention
management.

- The PHY DVDD can be connected to a always-on regulator unlike
previous targets where it is connected to either vddcx/vddmx.
qcom,phy-dvdd-always-on is passed from dtsi to indicate this
configuration to the driver. In this case, PHY can keep the
D+ pull-up during peripheral bus suspend without any board re-work.
The D+ and D- pull-down are also enabled during host bus suspend.

- The charger detection procedures are exactly the same except
data contact detection (DCD). The Idp_src and Rdm_down are de-coupled
in the Femto PHY. When DCD is enabled, the Idp_src alone is enabled
without enabling the Rdm_down resistors. Hence enable the Rdm_down
explicitly after enabling the DCD.

Change-Id: I381ded8ed2e739120923b337ab24059e45bf33aa
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>