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Commit b7f35903 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

ARM: msm: Properly switch secondary CPUs into THUMB2 mode



The kernel is always entered into in ARM mode to keep things
simple. The secondary CPU entry points were assuming that the
kernel is always compiled for ARM mode but it's possible to
compile the kernel for THUMB2 mode. Switch into THUMB2 mode as
early as possible in the secondary CPU entry points.

Change-Id: I918c207ea167d044ab3552b6ea608d3b9f2fbcf6
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 556bdeb6
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+6 −0
Original line number Diff line number Diff line
@@ -10,6 +10,8 @@
#include <linux/linkage.h>
#include <linux/init.h>

	.arm

__CPUINIT

/*
@@ -20,6 +22,10 @@ __CPUINIT
 * This is executing in physical space with cache's off.
 */
ENTRY(msm_secondary_startup)
THUMB(	adr	r9, BSYM(2f)	)	@ Kernel is always entered in ARM.
THUMB(	bx	r9		)	@ If this is a Thumb-2 kernel,
THUMB(	.thumb			)	@ switch to Thumb now.
THUMB(2:			)
	mrc	p15, 0, r0, c0, c0, 5 	@ MPIDR
	and	r0, r0, #15		@ What CPU am I
	adr	r4, 1f			@ address of
+6 −0
Original line number Diff line number Diff line
@@ -436,7 +436,13 @@ msm_pm_pa_to_va:
1:	b       1b
ENDPROC(msm_pm_collapse_exit)

	.arm

ENTRY(msm_pm_boot_entry)
THUMB(	adr	r9, BSYM(2f)	)	/* Kernel is always entered in ARM. */
THUMB(	bx	r9		)	/* If this is a Thumb-2 kernel, */
THUMB(	.thumb			)	/* switch to Thumb now.		*/
THUMB(2:			)
	mrc     p15, 0, r0, c0, c0, 5    /* MPIDR                          */
	and     r0, r0, #15              /* what CPU am I                  */