Loading Makefile +1 −1 Original line number Diff line number Diff line VERSION = 3 PATCHLEVEL = 10 SUBLEVEL = 81 SUBLEVEL = 82 EXTRAVERSION = NAME = TOSSUG Baby Fish Loading drivers/crypto/caam/caamrng.c +1 −1 Original line number Diff line number Diff line Loading @@ -56,7 +56,7 @@ /* Buffer, its dma address and lock */ struct buf_data { u8 buf[RN_BUF_SIZE]; u8 buf[RN_BUF_SIZE] ____cacheline_aligned; dma_addr_t addr; struct completion filled; u32 hw_desc[DESC_JOB_O_LEN]; Loading drivers/gpu/drm/mgag200/mgag200_mode.c +5 −0 Original line number Diff line number Diff line Loading @@ -1487,6 +1487,11 @@ static int mga_vga_mode_valid(struct drm_connector *connector, return MODE_BANDWIDTH; } if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 || (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) { return MODE_H_ILLEGAL; } if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 || mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 || mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 || Loading drivers/scsi/lpfc/lpfc_sli.c +21 −0 Original line number Diff line number Diff line Loading @@ -263,6 +263,16 @@ lpfc_sli4_eq_get(struct lpfc_queue *q) return NULL; q->hba_index = idx; /* * insert barrier for instruction interlock : data from the hardware * must have the valid bit checked before it can be copied and acted * upon. Given what was seen in lpfc_sli4_cq_get() of speculative * instructions allowing action on content before valid bit checked, * add barrier here as well. May not be needed as "content" is a * single 32-bit entity here (vs multi word structure for cq's). */ mb(); return eqe; } Loading Loading @@ -368,6 +378,17 @@ lpfc_sli4_cq_get(struct lpfc_queue *q) cqe = q->qe[q->hba_index].cqe; q->hba_index = idx; /* * insert barrier for instruction interlock : data from the hardware * must have the valid bit checked before it can be copied and acted * upon. Speculative instructions were allowing a bcopy at the start * of lpfc_sli4_fp_handle_wcqe(), which is called immediately * after our return, to copy data before the valid bit check above * was done. As such, some of the copied data was stale. The barrier * ensures the check is before any data is copied. */ mb(); return cqe; } Loading fs/pipe.c +0 −1 Original line number Diff line number Diff line Loading @@ -440,7 +440,6 @@ redo: break; } ret += chars; buf->offset += chars; buf->len -= chars; /* Was it a packet buffer? Clean up and exit */ Loading Loading
Makefile +1 −1 Original line number Diff line number Diff line VERSION = 3 PATCHLEVEL = 10 SUBLEVEL = 81 SUBLEVEL = 82 EXTRAVERSION = NAME = TOSSUG Baby Fish Loading
drivers/crypto/caam/caamrng.c +1 −1 Original line number Diff line number Diff line Loading @@ -56,7 +56,7 @@ /* Buffer, its dma address and lock */ struct buf_data { u8 buf[RN_BUF_SIZE]; u8 buf[RN_BUF_SIZE] ____cacheline_aligned; dma_addr_t addr; struct completion filled; u32 hw_desc[DESC_JOB_O_LEN]; Loading
drivers/gpu/drm/mgag200/mgag200_mode.c +5 −0 Original line number Diff line number Diff line Loading @@ -1487,6 +1487,11 @@ static int mga_vga_mode_valid(struct drm_connector *connector, return MODE_BANDWIDTH; } if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 || (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) { return MODE_H_ILLEGAL; } if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 || mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 || mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 || Loading
drivers/scsi/lpfc/lpfc_sli.c +21 −0 Original line number Diff line number Diff line Loading @@ -263,6 +263,16 @@ lpfc_sli4_eq_get(struct lpfc_queue *q) return NULL; q->hba_index = idx; /* * insert barrier for instruction interlock : data from the hardware * must have the valid bit checked before it can be copied and acted * upon. Given what was seen in lpfc_sli4_cq_get() of speculative * instructions allowing action on content before valid bit checked, * add barrier here as well. May not be needed as "content" is a * single 32-bit entity here (vs multi word structure for cq's). */ mb(); return eqe; } Loading Loading @@ -368,6 +378,17 @@ lpfc_sli4_cq_get(struct lpfc_queue *q) cqe = q->qe[q->hba_index].cqe; q->hba_index = idx; /* * insert barrier for instruction interlock : data from the hardware * must have the valid bit checked before it can be copied and acted * upon. Speculative instructions were allowing a bcopy at the start * of lpfc_sli4_fp_handle_wcqe(), which is called immediately * after our return, to copy data before the valid bit check above * was done. As such, some of the copied data was stale. The barrier * ensures the check is before any data is copied. */ mb(); return cqe; } Loading
fs/pipe.c +0 −1 Original line number Diff line number Diff line Loading @@ -440,7 +440,6 @@ redo: break; } ret += chars; buf->offset += chars; buf->len -= chars; /* Was it a packet buffer? Clean up and exit */ Loading