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Commit a854f839 authored by Dov Levenglick's avatar Dov Levenglick
Browse files

usb: phy: qmp: configure PCIE_USB3_PHY_FLL_CNTRL2 



This change is necessary to ensure that the FLL will operate
correctly across PVT.

CRs-Fixed: 717874
Change-Id: Iaecabd57ffe76141a040542fc186146d870875ec
Signed-off-by: default avatarDov Levenglick <dovl@codeaurora.org>
parent 76a0a75b

drivers/usb/phy/phy-msm-ssusb-qmp.c

+2 −0
Original line number Diff line number Diff line
@@ -113,6 +113,7 @@ static const struct qmp_reg_val qmp_settings_rev0[] = { 
	{0x6A0, 0x13}, /* PCIE_USB3_PHY_RXEQTRAINING_RUN_TIME */

	{0x66C, 0xFF}, /* PCIE_USB3_PHY_LOCK_DETECT_CONFIG1 */

	{0x674, 0x17}, /* PCIE_USB3_PHY_LOCK_DETECT_CONFIG3 */

	{0x6AC, 0x05}, /* PCIE_USB3_PHY_FLL_CNTRL2 */



	{-1, -1} /* terminating entry */

};
@@ -173,6 +174,7 @@ static const struct qmp_reg_val qmp_settings_rev1[] = { 
	{0x6A0, 0x13}, /* PCIE_USB3_PHY_RXEQTRAINING_RUN_TIME */

	{0x66C, 0xFF}, /* PCIE_USB3_PHY_LOCK_DETECT_CONFIG1 */

	{0x674, 0x17}, /* PCIE_USB3_PHY_LOCK_DETECT_CONFIG3 */

	{0x6AC, 0x05}, /* PCIE_USB3_PHY_FLL_CNTRL2 */



	{-1, -1} /* terminating entry */

};