Loading arch/arm/boot/dts/qcom/msm8916-coresight.dtsi +3 −0 Original line number Diff line number Diff line Loading @@ -180,6 +180,9 @@ coresight-outports = <0>; coresight-child-list = <&funnel_in0>; coresight-child-ports = <7>; qcom,data-barrier; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading arch/arm/boot/dts/qcom/msm8936-coresight.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -261,6 +261,8 @@ coresight-child-list = <&funnel_in0>; coresight-child-ports = <7>; qcom,data-barrier; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading arch/arm/boot/dts/qcom/msm8939-coresight.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -189,6 +189,8 @@ coresight-child-list = <&funnel_in0>; coresight-child-ports = <7>; qcom,data-barrier; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading arch/arm/boot/dts/qcom/msm8994-coresight-v1.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -197,6 +197,8 @@ coresight-child-list = <&funnel_in0>; coresight-child-ports = <7>; qcom,data-barrier; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading arch/arm/boot/dts/qcom/msm8994-coresight-v2.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -253,6 +253,8 @@ coresight-child-list = <&funnel_in0>; coresight-child-ports = <7>; qcom,data-barrier; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading Loading
arch/arm/boot/dts/qcom/msm8916-coresight.dtsi +3 −0 Original line number Diff line number Diff line Loading @@ -180,6 +180,9 @@ coresight-outports = <0>; coresight-child-list = <&funnel_in0>; coresight-child-ports = <7>; qcom,data-barrier; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading
arch/arm/boot/dts/qcom/msm8936-coresight.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -261,6 +261,8 @@ coresight-child-list = <&funnel_in0>; coresight-child-ports = <7>; qcom,data-barrier; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading
arch/arm/boot/dts/qcom/msm8939-coresight.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -189,6 +189,8 @@ coresight-child-list = <&funnel_in0>; coresight-child-ports = <7>; qcom,data-barrier; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading
arch/arm/boot/dts/qcom/msm8994-coresight-v1.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -197,6 +197,8 @@ coresight-child-list = <&funnel_in0>; coresight-child-ports = <7>; qcom,data-barrier; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading
arch/arm/boot/dts/qcom/msm8994-coresight-v2.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -253,6 +253,8 @@ coresight-child-list = <&funnel_in0>; coresight-child-ports = <7>; qcom,data-barrier; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading