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Commit 99b16ba9 authored by Junjie Wu's avatar Junjie Wu
Browse files

clock-plutonium: Model GPLL0 gating from GCC to MMSS 



MMSS needs to vote enable one bit in GCC before GPLL0 signal is propagated
to MMSS clock controller. Model this bit as a gate clock.

Change-Id: Iff8a228655cb778e4cc880ce9693ac756d41dda0
Signed-off-by: default avatarJunjie Wu <junjiew@codeaurora.org>
parent aeccbbdc

arch/arm/boot/dts/qcom/msmplutonium.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -417,7 +417,7 @@ 
		vdd_dig-supply = <&pmplutonium_s1_corner>;

		clock-names = "xo", "gpll0", "mmssnoc_ahb";

		clocks = <&clock_rpm clk_cxo_mmss>,

		         <&clock_gcc clk_gpll0_out_main>,

		         <&clock_gcc clk_gpll0_out_mmsscc>,

			 <&clock_rpm clk_mmssnoc_ahb_clk>;

		#clock-cells = <1>;

	};

drivers/clk/qcom/clock-gcc-plutonium.c

+17 −8
Original line number Diff line number Diff line
@@ -246,7 +246,6 @@ static struct pll_vote_clk gpll0 = { 
		CLK_INIT(gpll0.c),

	},

};

DEFINE_EXT_CLK(gpll0_out_main, &gpll0.c);



static struct pll_vote_clk gpll0_ao = {

	.en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
@@ -265,6 +264,8 @@ static struct pll_vote_clk gpll0_ao = { 
	},

};



DEFINE_EXT_CLK(gpll0_out_main, &gpll0.c);



static struct pll_vote_clk gpll4 = {

	.en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,

	.en_mask = BIT(4),
@@ -1208,6 +1209,19 @@ static struct rcg_clk usb_hs_system_clk_src = { 
	},

};



static struct gate_clk gpll0_out_mmsscc = {

	.en_reg = APCS_CLOCK_BRANCH_ENA_VOTE,

	.en_mask = BIT(26),

	.delay_us = 1,

	.base = &virt_base,

	.c = {

		.parent = &gpll0_out_main.c,

		.dbg_name = "gpll0_out_mmsscc",

		.ops = &clk_ops_gate,

		CLK_INIT(gpll0_out_mmsscc.c),

	},

};



static struct gate_clk pcie_0_phy_ldo = {

	.en_reg = PCIE_0_PHY_LDO_EN,

	.en_mask = BIT(0),
@@ -2423,8 +2437,8 @@ static struct clk_lookup msm_clocks_gcc_plutonium[] = { 
	CLK_LIST(debug_mmss_clk),

	CLK_LIST(debug_rpm_clk),

	CLK_LIST(gpll0),

	CLK_LIST(gpll0_out_main),

	CLK_LIST(gpll0_ao),

	CLK_LIST(gpll0_out_main),

	CLK_LIST(gpll4),

	CLK_LIST(gpll4_out_main),

	CLK_LIST(ufs_axi_clk_src),
@@ -2481,6 +2495,7 @@ static struct clk_lookup msm_clocks_gcc_plutonium[] = { 
	CLK_LIST(usb30_mock_utmi_clk_src),

	CLK_LIST(usb3_phy_aux_clk_src),

	CLK_LIST(usb_hs_system_clk_src),

	CLK_LIST(gpll0_out_mmsscc),

	CLK_LIST(pcie_0_phy_ldo),

	CLK_LIST(pcie_1_phy_ldo),

	CLK_LIST(ufs_phy_ldo),
@@ -2579,7 +2594,6 @@ static int msm_gcc_plutonium_probe(struct platform_device *pdev) 
{

	struct resource *res;

	struct clk *tmp_clk;

	u32 regval;

	int ret;



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base");
@@ -2614,11 +2628,6 @@ static int msm_gcc_plutonium_probe(struct platform_device *pdev) 
		return PTR_ERR(tmp_clk);

	}



	/* Vote for LPASS and MMSS controller to use GPLL0 */

	regval = readl_relaxed(GCC_REG_BASE(APCS_CLOCK_BRANCH_ENA_VOTE));

	writel_relaxed(regval | BIT(26),

		       GCC_REG_BASE(APCS_CLOCK_BRANCH_ENA_VOTE));



	ret = of_msm_clock_register(pdev->dev.of_node, msm_clocks_gcc_plutonium,

				    ARRAY_SIZE(msm_clocks_gcc_plutonium));

	if (ret)

include/dt-bindings/clock/msm-clocks-plutonium.h

+2 −1
Original line number Diff line number Diff line
@@ -99,8 +99,8 @@ 
#define clk_debug_mmss_clk 0x977c99b6

#define clk_debug_rpm_clk 0x8e2b07ca

#define clk_gpll0 0x1ebe3bc4

#define clk_gpll0_out_main 0xe9374de7

#define clk_gpll0_ao 0xa1368304

#define clk_gpll0_out_main 0xe9374de7

#define clk_gpll4 0xb3b5d85b

#define clk_gpll4_out_main 0xa9a0ab9d

#define clk_ufs_axi_clk_src 0x297ca380
@@ -157,6 +157,7 @@ 
#define clk_usb30_mock_utmi_clk_src 0xa024a976

#define clk_usb3_phy_aux_clk_src 0x15eec63c

#define clk_usb_hs_system_clk_src 0x28385546

#define clk_gpll0_out_mmsscc 0x0ded70aa

#define clk_pcie_0_phy_ldo 0x1d30d092

#define clk_pcie_1_phy_ldo 0x63474b42

#define clk_ufs_phy_ldo 0x98111fee