Loading arch/arm/boot/dts/msm9625-coresight.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -270,13 +270,13 @@ coresight-nr-inports = <0>; }; cti_cpu: cti@fc333000 { cti_cpu0: cti@fc333000 { compatible = "arm,coresight-cti"; reg = <0xfc333000 0x1000>; reg-names = "cti-base"; coresight-id = <22>; coresight-name = "coresight-cti-cpu"; coresight-name = "coresight-cti-cpu0"; coresight-nr-inports = <0>; }; Loading Loading
arch/arm/boot/dts/msm9625-coresight.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -270,13 +270,13 @@ coresight-nr-inports = <0>; }; cti_cpu: cti@fc333000 { cti_cpu0: cti@fc333000 { compatible = "arm,coresight-cti"; reg = <0xfc333000 0x1000>; reg-names = "cti-base"; coresight-id = <22>; coresight-name = "coresight-cti-cpu"; coresight-name = "coresight-cti-cpu0"; coresight-nr-inports = <0>; }; Loading