Commit 952f6091 authored Mar 25, 2014 by Padmanabhan Komanduru

clk: qcom: 8916: register DSI root clocks during gcc_mdss_probe



Currently the DSI RCG clocks are registered during gcc_probe
before the parents of these clocks are set during the
gcc_mdss_probe. This causes the clock handoff of the DSI
PLL clocks to not happen properly causing the DSI PLL
to get shutdown during the clock_late_init. The DSI PLL clocks
needed to stay enabled during boot up for continuous splash
screen feature. Hence, register these clocks during
gcc_mdss_probe after the parents of these clocks are set.

Change-Id: I4584f80454266e77fc3e15188ea164282b97458d
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>

parent 93980fdb

drivers/clk/qcom/clock-gcc-8916.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -2597,9 +2597,7 @@ static struct clk_lookup msm_clocks_lookup[] = {
		CLK_LIST(gp1_clk_src),
		CLK_LIST(gp2_clk_src),
		CLK_LIST(gp3_clk_src),
		CLK_LIST(byte0_clk_src),
		CLK_LIST(esc0_clk_src),
		CLK_LIST(pclk0_clk_src),
		CLK_LIST(vsync_clk_src),
		CLK_LIST(pdm2_clk_src),
		CLK_LIST(sdcc1_apps_clk_src),
		@@ -2895,6 +2893,8 @@ late_initcall(msm_clock_debug_init);

		/* MDSS DSI_PHY_PLL */
		static struct clk_lookup msm_clocks_gcc_mdss[] = {
		CLK_LIST(byte0_clk_src),
		CLK_LIST(pclk0_clk_src),
		CLK_LIST(gcc_mdss_pclk0_clk),
		CLK_LIST(gcc_mdss_byte0_clk),
		};