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Commit 9306c8de authored by Tim Anderson's avatar Tim Anderson Committed by Ralf Baechle
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MIPS: CMP: Extend the GIC IPI interrupts beyond 32 



This patch extends the GIC interrupt handling beyond the current 32 bit
range as well as extending the number of interrupts based on the number
of CPUs.

Signed-off-by: default avatarTim Anderson <tanderson@mvista.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent b53d4d1f

arch/mips/include/asm/gic.h

+4 −0
Original line number Diff line number Diff line
@@ -20,7 +20,11 @@ 
#define GIC_TRIG_EDGE			1

#define GIC_TRIG_LEVEL			0



#if CONFIG_SMP

#define GIC_NUM_INTRS			(24 + NR_CPUS * 2)

#else

#define GIC_NUM_INTRS			32

#endif



#define MSK(n) ((1 << (n)) - 1)

#define REG32(addr)		(*(volatile unsigned int *) (addr))

arch/mips/kernel/irq-gic.c

+4 −11
Original line number Diff line number Diff line
@@ -107,9 +107,7 @@ static unsigned int gic_irq_startup(unsigned int irq) 
{

	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);

	irq -= _irqbase;

	/* FIXME: this is wrong for !GICISWORDLITTLEENDIAN */

	GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_SMASK_31_0_OFS + (irq / 32))),

		 1 << (irq % 32));

	GIC_SET_INTR_MASK(irq, 1);

	return 0;

}
@@ -120,8 +118,7 @@ static void gic_irq_ack(unsigned int irq) 
#endif

	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);

	irq -= _irqbase;

	GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_RMASK_31_0_OFS + (irq / 32))),

		 1 << (irq % 32));

	GIC_CLR_INTR_MASK(irq, 1);



	if (_intrmap[irq].trigtype == GIC_TRIG_EDGE) {

		if (!gic_wedgeb2bok)
@@ -138,18 +135,14 @@ static void gic_mask_irq(unsigned int irq) 
{

	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);

	irq -= _irqbase;

	/* FIXME: this is wrong for !GICISWORDLITTLEENDIAN */

	GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_RMASK_31_0_OFS + (irq / 32))),

		 1 << (irq % 32));

	GIC_CLR_INTR_MASK(irq, 1);

}



static void gic_unmask_irq(unsigned int irq)

{

	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);

	irq -= _irqbase;

	/* FIXME: this is wrong for !GICISWORDLITTLEENDIAN */

	GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_SMASK_31_0_OFS + (irq / 32))),

		 1 << (irq % 32));

	GIC_SET_INTR_MASK(irq, 1);

}



#ifdef CONFIG_SMP