Loading drivers/clk/qcom/clock-gcc-8994.c +5 −0 Original line number Diff line number Diff line Loading @@ -1989,6 +1989,7 @@ static struct branch_clk gcc_lpass_q6_axi_clk = { .cbcr_reg = LPASS_Q6_AXI_CBCR, .has_sibling = 1, .base = &virt_base, .halt_check = DELAY, .c = { .dbg_name = "gcc_lpass_q6_axi_clk", .ops = &clk_ops_branch, Loading Loading @@ -2351,6 +2352,7 @@ static struct branch_clk gcc_ufs_rx_symbol_0_clk = { .cbcr_reg = UFS_RX_SYMBOL_0_CBCR, .has_sibling = 1, .base = &virt_base, .halt_check = DELAY, .c = { .dbg_name = "gcc_ufs_rx_symbol_0_clk", .ops = &clk_ops_branch, Loading @@ -2362,6 +2364,7 @@ static struct branch_clk gcc_ufs_rx_symbol_1_clk = { .cbcr_reg = UFS_RX_SYMBOL_1_CBCR, .has_sibling = 1, .base = &virt_base, .halt_check = DELAY, .c = { .dbg_name = "gcc_ufs_rx_symbol_1_clk", .ops = &clk_ops_branch, Loading @@ -2387,6 +2390,7 @@ static struct branch_clk gcc_ufs_tx_symbol_0_clk = { .cbcr_reg = UFS_TX_SYMBOL_0_CBCR, .has_sibling = 1, .base = &virt_base, .halt_check = DELAY, .c = { .dbg_name = "gcc_ufs_tx_symbol_0_clk", .ops = &clk_ops_branch, Loading @@ -2398,6 +2402,7 @@ static struct branch_clk gcc_ufs_tx_symbol_1_clk = { .cbcr_reg = UFS_TX_SYMBOL_1_CBCR, .has_sibling = 1, .base = &virt_base, .halt_check = DELAY, .c = { .dbg_name = "gcc_ufs_tx_symbol_1_clk", .ops = &clk_ops_branch, Loading Loading
drivers/clk/qcom/clock-gcc-8994.c +5 −0 Original line number Diff line number Diff line Loading @@ -1989,6 +1989,7 @@ static struct branch_clk gcc_lpass_q6_axi_clk = { .cbcr_reg = LPASS_Q6_AXI_CBCR, .has_sibling = 1, .base = &virt_base, .halt_check = DELAY, .c = { .dbg_name = "gcc_lpass_q6_axi_clk", .ops = &clk_ops_branch, Loading Loading @@ -2351,6 +2352,7 @@ static struct branch_clk gcc_ufs_rx_symbol_0_clk = { .cbcr_reg = UFS_RX_SYMBOL_0_CBCR, .has_sibling = 1, .base = &virt_base, .halt_check = DELAY, .c = { .dbg_name = "gcc_ufs_rx_symbol_0_clk", .ops = &clk_ops_branch, Loading @@ -2362,6 +2364,7 @@ static struct branch_clk gcc_ufs_rx_symbol_1_clk = { .cbcr_reg = UFS_RX_SYMBOL_1_CBCR, .has_sibling = 1, .base = &virt_base, .halt_check = DELAY, .c = { .dbg_name = "gcc_ufs_rx_symbol_1_clk", .ops = &clk_ops_branch, Loading @@ -2387,6 +2390,7 @@ static struct branch_clk gcc_ufs_tx_symbol_0_clk = { .cbcr_reg = UFS_TX_SYMBOL_0_CBCR, .has_sibling = 1, .base = &virt_base, .halt_check = DELAY, .c = { .dbg_name = "gcc_ufs_tx_symbol_0_clk", .ops = &clk_ops_branch, Loading @@ -2398,6 +2402,7 @@ static struct branch_clk gcc_ufs_tx_symbol_1_clk = { .cbcr_reg = UFS_TX_SYMBOL_1_CBCR, .has_sibling = 1, .base = &virt_base, .halt_check = DELAY, .c = { .dbg_name = "gcc_ufs_tx_symbol_1_clk", .ops = &clk_ops_branch, Loading