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Commit 678befa3 authored by Shubhraprakash Das's avatar Shubhraprakash Das
Browse files

msm: kgsl: Fix clock gate settings for A4XX 



The L1 clocking was not disabled completely for A420. CCU
caching feature requires the L1 clocking to be completely
disabled on A420 hardware as a h/w workaround.

Change-Id: I716d6133d80c912dd3f0d479babfc526f0e758ad
CRs-Fixed: 624275
Signed-off-by: default avatarShubhraprakash Das <sadas@codeaurora.org>
parent 500bff85

drivers/gpu/msm/adreno_a4xx.c

+9 −6
Original line number Diff line number Diff line
@@ -309,14 +309,17 @@ static void a4xx_enable_hwcg(struct kgsl_device *device) 
	kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_RB2, 0x22222222);

	kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_RB3, 0x22222222);

	/* Disable L1 clocking in A420 due to CCU issues with it */

	if (adreno_is_a420(adreno_dev))

	if (adreno_is_a420(adreno_dev)) {

		kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB0, 0x00002020);

	else

		kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB1, 0x00002020);

		kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB2, 0x00002020);

		kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB3, 0x00002020);

	} else {

		kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB0, 0x00022020);



		kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB1, 0x00022020);

		kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB2, 0x00022020);

		kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB3, 0x00022020);

	}

	kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_MARB_CCU0, 0x00000922);

	kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_MARB_CCU1, 0x00000922);

	kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_MARB_CCU2, 0x00000922);