Loading drivers/video/msm/mdss/mdp3_ctrl.c +5 −0 Original line number Diff line number Diff line Loading @@ -644,6 +644,8 @@ static int mdp3_ctrl_on(struct msm_fb_data_type *mfd) goto on_error; } mdp3_dma_pp_resume(mdp3_session->dma); rc = mdp3_ppp_init(); if (rc) { pr_err("ppp init failed\n"); Loading Loading @@ -1475,6 +1477,9 @@ static int mdp3_csc_config(struct mdp3_session_data *session, ccs.pre_lv = data->csc_data.csc_pre_lv; ccs.post_lv = data->csc_data.csc_post_lv; /* cache one copy of setting for suspend/resume reconfiguring */ session->dma->ccs_cache = *data; mutex_lock(&session->lock); mdp3_clk_enable(1, 0); ret = session->dma->config_ccs(session->dma, &config, &ccs); Loading drivers/video/msm/mdss/mdp3_dma.c +79 −43 Original line number Diff line number Diff line Loading @@ -452,46 +452,7 @@ static int mdp3_dmap_cursor_config(struct mdp3_dma *dma, return 0; } static void mdp3_ccs_update(struct mdp3_dma *dma) { u32 cc_config; int updated = 0; cc_config = MDP3_REG_READ(MDP3_REG_DMA_P_COLOR_CORRECT_CONFIG); if (dma->ccs_config.ccs_dirty) { cc_config &= DMA_CCS_CONFIG_MASK; if (dma->ccs_config.ccs_enable) cc_config |= BIT(3); else cc_config &= ~BIT(3); cc_config |= dma->ccs_config.ccs_sel << 5; cc_config |= dma->ccs_config.pre_bias_sel << 6; cc_config |= dma->ccs_config.post_bias_sel << 7; cc_config |= dma->ccs_config.pre_limit_sel << 8; cc_config |= dma->ccs_config.post_limit_sel << 9; dma->ccs_config.ccs_dirty = false; updated = 1; } if (dma->lut_config.lut_dirty) { cc_config &= DMA_LUT_CONFIG_MASK; cc_config |= dma->lut_config.lut_enable; cc_config |= dma->lut_config.lut_position << 4; cc_config |= dma->lut_config.lut_sel << 10; dma->lut_config.lut_dirty = false; updated = 1; } if (updated) { MDP3_REG_WRITE(MDP3_REG_DMA_P_COLOR_CORRECT_CONFIG, cc_config); /* Make sure ccs configuration update is done before continuing with the DMA transfer */ wmb(); } } static int mdp3_dmap_ccs_config(struct mdp3_dma *dma, static int mdp3_dmap_ccs_config_internal(struct mdp3_dma *dma, struct mdp3_dma_color_correct_config *config, struct mdp3_dma_ccs *ccs) { Loading Loading @@ -542,14 +503,89 @@ static int mdp3_dmap_ccs_config(struct mdp3_dma *dma, addr += 4; } } return 0; } static void mdp3_ccs_update(struct mdp3_dma *dma, bool from_kickoff) { u32 cc_config; int updated = 0; struct mdp3_dma_ccs ccs; cc_config = MDP3_REG_READ(MDP3_REG_DMA_P_COLOR_CORRECT_CONFIG); if (dma->ccs_config.ccs_dirty) { cc_config &= DMA_CCS_CONFIG_MASK; if (dma->ccs_config.ccs_enable) cc_config |= BIT(3); else cc_config &= ~BIT(3); cc_config |= dma->ccs_config.ccs_sel << 5; cc_config |= dma->ccs_config.pre_bias_sel << 6; cc_config |= dma->ccs_config.post_bias_sel << 7; cc_config |= dma->ccs_config.pre_limit_sel << 8; cc_config |= dma->ccs_config.post_limit_sel << 9; dma->ccs_config.ccs_dirty = false; updated = 1; } if (dma->lut_config.lut_dirty) { cc_config &= DMA_LUT_CONFIG_MASK; cc_config |= dma->lut_config.lut_enable; cc_config |= dma->lut_config.lut_position << 4; cc_config |= dma->lut_config.lut_sel << 10; dma->lut_config.lut_dirty = false; updated = 1; } if (updated) { if (from_kickoff) { ccs.mv = dma->ccs_cache.csc_data.csc_mv; ccs.pre_bv = dma->ccs_cache.csc_data.csc_pre_bv; ccs.post_bv = dma->ccs_cache.csc_data.csc_post_bv; ccs.pre_lv = dma->ccs_cache.csc_data.csc_pre_lv; ccs.post_lv = dma->ccs_cache.csc_data.csc_post_lv; mdp3_dmap_ccs_config_internal(dma, &dma->ccs_config, &ccs); } MDP3_REG_WRITE(MDP3_REG_DMA_P_COLOR_CORRECT_CONFIG, cc_config); /* * Make sure ccs configuration update is done before continuing * with the DMA transfer */ wmb(); } } static int mdp3_dmap_ccs_config(struct mdp3_dma *dma, struct mdp3_dma_color_correct_config *config, struct mdp3_dma_ccs *ccs) { mdp3_dmap_ccs_config_internal(dma, config, ccs); dma->ccs_config = *config; if (dma->output_config.out_sel != MDP3_DMA_OUTPUT_SEL_DSI_CMD) mdp3_ccs_update(dma); mdp3_ccs_update(dma, false); return 0; } /* Invoked from ctrl_on. */ void mdp3_dma_pp_resume(struct mdp3_dma *dma) { /* * if dma->ccs_config.ccs_enable is set then DMA PP block was enabled * via user space IOCTL. * Then set dma->ccs_config.ccs_dirty flag * Then PP block will be reconfigured when next kickoff comes. */ if (dma->ccs_config.ccs_enable) dma->ccs_config.ccs_dirty = true; } static int mdp3_dmap_lut_config(struct mdp3_dma *dma, struct mdp3_dma_lut_config *config, struct mdp3_dma_lut *lut) Loading @@ -574,7 +610,7 @@ static int mdp3_dmap_lut_config(struct mdp3_dma *dma, dma->lut_config = *config; if (dma->output_config.out_sel != MDP3_DMA_OUTPUT_SEL_DSI_CMD) mdp3_ccs_update(dma); mdp3_ccs_update(dma, false); return 0; } Loading Loading @@ -665,8 +701,8 @@ static int mdp3_dmap_update(struct mdp3_dma *dma, void *buf, dma->roi.y * dma->source_config.stride + dma->roi.x * dma_bpp(dma->source_config.format))); dma->source_config.buf = (int)buf; mdp3_ccs_update(dma, true); if (dma->output_config.out_sel == MDP3_DMA_OUTPUT_SEL_DSI_CMD) { mdp3_ccs_update(dma); MDP3_REG_WRITE(MDP3_REG_DMA_P_START, 1); } Loading drivers/video/msm/mdss/mdp3_dma.h +5 −0 Original line number Diff line number Diff line Loading @@ -16,6 +16,7 @@ #include <linux/notifier.h> #include <linux/sched.h> #include <linux/msm_mdp.h> #define MDP_HISTOGRAM_BL_SCALE_MAX 1024 #define MDP_HISTOGRAM_BL_LEVEL_MAX 255 Loading Loading @@ -274,6 +275,8 @@ struct mdp3_dma { struct mdp3_dma_cursor cursor; struct mdp3_dma_color_correct_config ccs_config; struct mdp_csc_cfg_data ccs_cache; struct mdp3_dma_lut_config lut_config; struct mdp3_dma_histogram_config histogram_config; int histo_state; Loading Loading @@ -372,6 +375,8 @@ struct mdp3_intf { int mdp3_dma_init(struct mdp3_dma *dma); void mdp3_dma_pp_resume(struct mdp3_dma *dma); int mdp3_intf_init(struct mdp3_intf *intf); void mdp3_dma_callback_enable(struct mdp3_dma *dma, int type); Loading Loading
drivers/video/msm/mdss/mdp3_ctrl.c +5 −0 Original line number Diff line number Diff line Loading @@ -644,6 +644,8 @@ static int mdp3_ctrl_on(struct msm_fb_data_type *mfd) goto on_error; } mdp3_dma_pp_resume(mdp3_session->dma); rc = mdp3_ppp_init(); if (rc) { pr_err("ppp init failed\n"); Loading Loading @@ -1475,6 +1477,9 @@ static int mdp3_csc_config(struct mdp3_session_data *session, ccs.pre_lv = data->csc_data.csc_pre_lv; ccs.post_lv = data->csc_data.csc_post_lv; /* cache one copy of setting for suspend/resume reconfiguring */ session->dma->ccs_cache = *data; mutex_lock(&session->lock); mdp3_clk_enable(1, 0); ret = session->dma->config_ccs(session->dma, &config, &ccs); Loading
drivers/video/msm/mdss/mdp3_dma.c +79 −43 Original line number Diff line number Diff line Loading @@ -452,46 +452,7 @@ static int mdp3_dmap_cursor_config(struct mdp3_dma *dma, return 0; } static void mdp3_ccs_update(struct mdp3_dma *dma) { u32 cc_config; int updated = 0; cc_config = MDP3_REG_READ(MDP3_REG_DMA_P_COLOR_CORRECT_CONFIG); if (dma->ccs_config.ccs_dirty) { cc_config &= DMA_CCS_CONFIG_MASK; if (dma->ccs_config.ccs_enable) cc_config |= BIT(3); else cc_config &= ~BIT(3); cc_config |= dma->ccs_config.ccs_sel << 5; cc_config |= dma->ccs_config.pre_bias_sel << 6; cc_config |= dma->ccs_config.post_bias_sel << 7; cc_config |= dma->ccs_config.pre_limit_sel << 8; cc_config |= dma->ccs_config.post_limit_sel << 9; dma->ccs_config.ccs_dirty = false; updated = 1; } if (dma->lut_config.lut_dirty) { cc_config &= DMA_LUT_CONFIG_MASK; cc_config |= dma->lut_config.lut_enable; cc_config |= dma->lut_config.lut_position << 4; cc_config |= dma->lut_config.lut_sel << 10; dma->lut_config.lut_dirty = false; updated = 1; } if (updated) { MDP3_REG_WRITE(MDP3_REG_DMA_P_COLOR_CORRECT_CONFIG, cc_config); /* Make sure ccs configuration update is done before continuing with the DMA transfer */ wmb(); } } static int mdp3_dmap_ccs_config(struct mdp3_dma *dma, static int mdp3_dmap_ccs_config_internal(struct mdp3_dma *dma, struct mdp3_dma_color_correct_config *config, struct mdp3_dma_ccs *ccs) { Loading Loading @@ -542,14 +503,89 @@ static int mdp3_dmap_ccs_config(struct mdp3_dma *dma, addr += 4; } } return 0; } static void mdp3_ccs_update(struct mdp3_dma *dma, bool from_kickoff) { u32 cc_config; int updated = 0; struct mdp3_dma_ccs ccs; cc_config = MDP3_REG_READ(MDP3_REG_DMA_P_COLOR_CORRECT_CONFIG); if (dma->ccs_config.ccs_dirty) { cc_config &= DMA_CCS_CONFIG_MASK; if (dma->ccs_config.ccs_enable) cc_config |= BIT(3); else cc_config &= ~BIT(3); cc_config |= dma->ccs_config.ccs_sel << 5; cc_config |= dma->ccs_config.pre_bias_sel << 6; cc_config |= dma->ccs_config.post_bias_sel << 7; cc_config |= dma->ccs_config.pre_limit_sel << 8; cc_config |= dma->ccs_config.post_limit_sel << 9; dma->ccs_config.ccs_dirty = false; updated = 1; } if (dma->lut_config.lut_dirty) { cc_config &= DMA_LUT_CONFIG_MASK; cc_config |= dma->lut_config.lut_enable; cc_config |= dma->lut_config.lut_position << 4; cc_config |= dma->lut_config.lut_sel << 10; dma->lut_config.lut_dirty = false; updated = 1; } if (updated) { if (from_kickoff) { ccs.mv = dma->ccs_cache.csc_data.csc_mv; ccs.pre_bv = dma->ccs_cache.csc_data.csc_pre_bv; ccs.post_bv = dma->ccs_cache.csc_data.csc_post_bv; ccs.pre_lv = dma->ccs_cache.csc_data.csc_pre_lv; ccs.post_lv = dma->ccs_cache.csc_data.csc_post_lv; mdp3_dmap_ccs_config_internal(dma, &dma->ccs_config, &ccs); } MDP3_REG_WRITE(MDP3_REG_DMA_P_COLOR_CORRECT_CONFIG, cc_config); /* * Make sure ccs configuration update is done before continuing * with the DMA transfer */ wmb(); } } static int mdp3_dmap_ccs_config(struct mdp3_dma *dma, struct mdp3_dma_color_correct_config *config, struct mdp3_dma_ccs *ccs) { mdp3_dmap_ccs_config_internal(dma, config, ccs); dma->ccs_config = *config; if (dma->output_config.out_sel != MDP3_DMA_OUTPUT_SEL_DSI_CMD) mdp3_ccs_update(dma); mdp3_ccs_update(dma, false); return 0; } /* Invoked from ctrl_on. */ void mdp3_dma_pp_resume(struct mdp3_dma *dma) { /* * if dma->ccs_config.ccs_enable is set then DMA PP block was enabled * via user space IOCTL. * Then set dma->ccs_config.ccs_dirty flag * Then PP block will be reconfigured when next kickoff comes. */ if (dma->ccs_config.ccs_enable) dma->ccs_config.ccs_dirty = true; } static int mdp3_dmap_lut_config(struct mdp3_dma *dma, struct mdp3_dma_lut_config *config, struct mdp3_dma_lut *lut) Loading @@ -574,7 +610,7 @@ static int mdp3_dmap_lut_config(struct mdp3_dma *dma, dma->lut_config = *config; if (dma->output_config.out_sel != MDP3_DMA_OUTPUT_SEL_DSI_CMD) mdp3_ccs_update(dma); mdp3_ccs_update(dma, false); return 0; } Loading Loading @@ -665,8 +701,8 @@ static int mdp3_dmap_update(struct mdp3_dma *dma, void *buf, dma->roi.y * dma->source_config.stride + dma->roi.x * dma_bpp(dma->source_config.format))); dma->source_config.buf = (int)buf; mdp3_ccs_update(dma, true); if (dma->output_config.out_sel == MDP3_DMA_OUTPUT_SEL_DSI_CMD) { mdp3_ccs_update(dma); MDP3_REG_WRITE(MDP3_REG_DMA_P_START, 1); } Loading
drivers/video/msm/mdss/mdp3_dma.h +5 −0 Original line number Diff line number Diff line Loading @@ -16,6 +16,7 @@ #include <linux/notifier.h> #include <linux/sched.h> #include <linux/msm_mdp.h> #define MDP_HISTOGRAM_BL_SCALE_MAX 1024 #define MDP_HISTOGRAM_BL_LEVEL_MAX 255 Loading Loading @@ -274,6 +275,8 @@ struct mdp3_dma { struct mdp3_dma_cursor cursor; struct mdp3_dma_color_correct_config ccs_config; struct mdp_csc_cfg_data ccs_cache; struct mdp3_dma_lut_config lut_config; struct mdp3_dma_histogram_config histogram_config; int histo_state; Loading Loading @@ -372,6 +375,8 @@ struct mdp3_intf { int mdp3_dma_init(struct mdp3_dma *dma); void mdp3_dma_pp_resume(struct mdp3_dma *dma); int mdp3_intf_init(struct mdp3_intf *intf); void mdp3_dma_callback_enable(struct mdp3_dma *dma, int type); Loading