Loading drivers/gpio/gpio-msm-v3.c +16 −16 Original line number Diff line number Diff line /* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. /* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -99,22 +99,22 @@ static unsigned subsys_id = 4; static inline void set_gpio_bits(unsigned n, void __iomem *reg) { __raw_writel(__raw_readl(reg) | n, reg); __raw_writel_no_log(__raw_readl_no_log(reg) | n, reg); } static inline void clr_gpio_bits(unsigned n, void __iomem *reg) { __raw_writel(__raw_readl(reg) & ~n, reg); __raw_writel_no_log(__raw_readl_no_log(reg) & ~n, reg); } unsigned __msm_gpio_get_inout(unsigned gpio) { return __raw_readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN_BIT); return __raw_readl_no_log(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN_BIT); } void __msm_gpio_set_inout(unsigned gpio, unsigned val) { __raw_writel(val ? BIT(GPIO_OUT_BIT) : 0, GPIO_IN_OUT(gpio)); __raw_writel_no_log(val ? BIT(GPIO_OUT_BIT) : 0, GPIO_IN_OUT(gpio)); } void __msm_gpio_set_config_direction(unsigned gpio, int input, int val) Loading @@ -137,32 +137,32 @@ void __msm_gpio_set_polarity(unsigned gpio, unsigned val) unsigned __msm_gpio_get_intr_status(unsigned gpio) { return __raw_readl(GPIO_INTR_STATUS(gpio)) & return __raw_readl_no_log(GPIO_INTR_STATUS(gpio)) & BIT(INTR_STATUS_BIT); } void __msm_gpio_set_intr_status(unsigned gpio) { __raw_writel(0, GPIO_INTR_STATUS(gpio)); __raw_writel_no_log(0, GPIO_INTR_STATUS(gpio)); } unsigned __msm_gpio_get_intr_config(unsigned gpio) { return __raw_readl(GPIO_INTR_CFG(gpio)); return __raw_readl_no_log(GPIO_INTR_CFG(gpio)); } void __msm_gpio_set_intr_cfg_enable(unsigned gpio, unsigned val) { unsigned cfg; cfg = __raw_readl(GPIO_INTR_CFG(gpio)); cfg = __raw_readl_no_log(GPIO_INTR_CFG(gpio)); if (val) { cfg &= ~INTR_DIR_CONN_EN; cfg |= INTR_ENABLE; } else { cfg &= ~INTR_ENABLE; } __raw_writel(cfg, GPIO_INTR_CFG(gpio)); __raw_writel_no_log(cfg, GPIO_INTR_CFG(gpio)); } unsigned __msm_gpio_get_intr_cfg_enable(unsigned gpio) Loading @@ -179,7 +179,7 @@ void __msm_gpio_set_intr_cfg_type(unsigned gpio, unsigned type) * could cause the INTR_STATUS to be set for EDGE interrupts. */ cfg = INTR_RAW_STATUS_EN | INTR_TARGET_PROC_APPS; __raw_writel(cfg, GPIO_INTR_CFG(gpio)); __raw_writel_no_log(cfg, GPIO_INTR_CFG(gpio)); cfg &= ~INTR_DECT_CTL_MASK; if (type == IRQ_TYPE_EDGE_RISING) cfg |= INTR_DECT_CTL_POS_EDGE; Loading @@ -195,7 +195,7 @@ void __msm_gpio_set_intr_cfg_type(unsigned gpio, unsigned type) else cfg |= INTR_POL_CTL_HI; __raw_writel(cfg, GPIO_INTR_CFG(gpio)); __raw_writel_no_log(cfg, GPIO_INTR_CFG(gpio)); /* Sometimes it might take a little while to update * the interrupt status after the RAW_STATUS is enabled * We clear the interrupt status before enabling the Loading @@ -218,7 +218,7 @@ void __gpio_tlmm_config(unsigned config) ((GPIO_DRVSTR(config) << 6) & (0x7 << 6)) | ((GPIO_FUNC(config) << 2) & (0xf << 2)) | ((GPIO_PULL(config) & 0x3)); __raw_writel(flags, GPIO_CONFIG(gpio)); __raw_writel_no_log(flags, GPIO_CONFIG(gpio)); } void __msm_gpio_install_direct_irq(unsigned gpio, unsigned irq, Loading @@ -227,13 +227,13 @@ void __msm_gpio_install_direct_irq(unsigned gpio, unsigned irq, unsigned cfg; set_gpio_bits(BIT(GPIO_OE_BIT), GPIO_CONFIG(gpio)); cfg = __raw_readl(GPIO_INTR_CFG(gpio)); cfg = __raw_readl_no_log(GPIO_INTR_CFG(gpio)); cfg &= ~(INTR_TARGET_PROC_NONE | INTR_RAW_STATUS_EN | INTR_ENABLE); cfg |= INTR_TARGET_PROC_APPS | INTR_DIR_CONN_EN; __raw_writel(cfg, GPIO_INTR_CFG(gpio)); __raw_writel_no_log(cfg, GPIO_INTR_CFG(gpio)); cfg = gpio; if (input_polarity) cfg |= DC_POLARITY_HI; __raw_writel(cfg, GPIO_DIR_CONN_INTR(irq)); __raw_writel_no_log(cfg, GPIO_DIR_CONN_INTR(irq)); } Loading
drivers/gpio/gpio-msm-v3.c +16 −16 Original line number Diff line number Diff line /* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. /* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -99,22 +99,22 @@ static unsigned subsys_id = 4; static inline void set_gpio_bits(unsigned n, void __iomem *reg) { __raw_writel(__raw_readl(reg) | n, reg); __raw_writel_no_log(__raw_readl_no_log(reg) | n, reg); } static inline void clr_gpio_bits(unsigned n, void __iomem *reg) { __raw_writel(__raw_readl(reg) & ~n, reg); __raw_writel_no_log(__raw_readl_no_log(reg) & ~n, reg); } unsigned __msm_gpio_get_inout(unsigned gpio) { return __raw_readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN_BIT); return __raw_readl_no_log(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN_BIT); } void __msm_gpio_set_inout(unsigned gpio, unsigned val) { __raw_writel(val ? BIT(GPIO_OUT_BIT) : 0, GPIO_IN_OUT(gpio)); __raw_writel_no_log(val ? BIT(GPIO_OUT_BIT) : 0, GPIO_IN_OUT(gpio)); } void __msm_gpio_set_config_direction(unsigned gpio, int input, int val) Loading @@ -137,32 +137,32 @@ void __msm_gpio_set_polarity(unsigned gpio, unsigned val) unsigned __msm_gpio_get_intr_status(unsigned gpio) { return __raw_readl(GPIO_INTR_STATUS(gpio)) & return __raw_readl_no_log(GPIO_INTR_STATUS(gpio)) & BIT(INTR_STATUS_BIT); } void __msm_gpio_set_intr_status(unsigned gpio) { __raw_writel(0, GPIO_INTR_STATUS(gpio)); __raw_writel_no_log(0, GPIO_INTR_STATUS(gpio)); } unsigned __msm_gpio_get_intr_config(unsigned gpio) { return __raw_readl(GPIO_INTR_CFG(gpio)); return __raw_readl_no_log(GPIO_INTR_CFG(gpio)); } void __msm_gpio_set_intr_cfg_enable(unsigned gpio, unsigned val) { unsigned cfg; cfg = __raw_readl(GPIO_INTR_CFG(gpio)); cfg = __raw_readl_no_log(GPIO_INTR_CFG(gpio)); if (val) { cfg &= ~INTR_DIR_CONN_EN; cfg |= INTR_ENABLE; } else { cfg &= ~INTR_ENABLE; } __raw_writel(cfg, GPIO_INTR_CFG(gpio)); __raw_writel_no_log(cfg, GPIO_INTR_CFG(gpio)); } unsigned __msm_gpio_get_intr_cfg_enable(unsigned gpio) Loading @@ -179,7 +179,7 @@ void __msm_gpio_set_intr_cfg_type(unsigned gpio, unsigned type) * could cause the INTR_STATUS to be set for EDGE interrupts. */ cfg = INTR_RAW_STATUS_EN | INTR_TARGET_PROC_APPS; __raw_writel(cfg, GPIO_INTR_CFG(gpio)); __raw_writel_no_log(cfg, GPIO_INTR_CFG(gpio)); cfg &= ~INTR_DECT_CTL_MASK; if (type == IRQ_TYPE_EDGE_RISING) cfg |= INTR_DECT_CTL_POS_EDGE; Loading @@ -195,7 +195,7 @@ void __msm_gpio_set_intr_cfg_type(unsigned gpio, unsigned type) else cfg |= INTR_POL_CTL_HI; __raw_writel(cfg, GPIO_INTR_CFG(gpio)); __raw_writel_no_log(cfg, GPIO_INTR_CFG(gpio)); /* Sometimes it might take a little while to update * the interrupt status after the RAW_STATUS is enabled * We clear the interrupt status before enabling the Loading @@ -218,7 +218,7 @@ void __gpio_tlmm_config(unsigned config) ((GPIO_DRVSTR(config) << 6) & (0x7 << 6)) | ((GPIO_FUNC(config) << 2) & (0xf << 2)) | ((GPIO_PULL(config) & 0x3)); __raw_writel(flags, GPIO_CONFIG(gpio)); __raw_writel_no_log(flags, GPIO_CONFIG(gpio)); } void __msm_gpio_install_direct_irq(unsigned gpio, unsigned irq, Loading @@ -227,13 +227,13 @@ void __msm_gpio_install_direct_irq(unsigned gpio, unsigned irq, unsigned cfg; set_gpio_bits(BIT(GPIO_OE_BIT), GPIO_CONFIG(gpio)); cfg = __raw_readl(GPIO_INTR_CFG(gpio)); cfg = __raw_readl_no_log(GPIO_INTR_CFG(gpio)); cfg &= ~(INTR_TARGET_PROC_NONE | INTR_RAW_STATUS_EN | INTR_ENABLE); cfg |= INTR_TARGET_PROC_APPS | INTR_DIR_CONN_EN; __raw_writel(cfg, GPIO_INTR_CFG(gpio)); __raw_writel_no_log(cfg, GPIO_INTR_CFG(gpio)); cfg = gpio; if (input_polarity) cfg |= DC_POLARITY_HI; __raw_writel(cfg, GPIO_DIR_CONN_INTR(irq)); __raw_writel_no_log(cfg, GPIO_DIR_CONN_INTR(irq)); }