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Commit 3ae81d47 authored by Ujwal Patel's avatar Ujwal Patel
Browse files

msm: mdss: enable synchronous flush only for video mode panels 



Synchronous flush should not be used on command mode panels. If used,
as done in current implementation, it will only generate start signal
to left ctl path, and right ctl path will never receive start signal.
This leads to right half of the display to be blank. Fix this by
enabling synchronous flush only for video mode panels.

Change-Id: I9d950febcd0b5c046f6461dbb0a1f99208b93f06
Signed-off-by: default avatarUjwal Patel <ujwalp@codeaurora.org>
parent f28186f6

drivers/video/msm/mdss/mdss_mdp.h

+1 −0
Original line number Diff line number Diff line
@@ -154,6 +154,7 @@ struct mdss_mdp_ctl { 
	u32 flush_bits;

	u32 flush_reg_data;



	bool split_flush_en;

	bool is_video_mode;

	u32 play_cnt;

	u32 vsync_cnt;

drivers/video/msm/mdss/mdss_mdp_ctl.c

+9 −3
Original line number Diff line number Diff line
@@ -656,13 +656,19 @@ int mdss_mdp_ctl_splash_finish(struct mdss_mdp_ctl *ctl, bool handoff) 
static inline int mdss_mdp_set_split_ctl(struct mdss_mdp_ctl *ctl,

		struct mdss_mdp_ctl *split_ctl)

{

	if (!ctl || !split_ctl)

	struct mdss_data_type *mdata = mdss_mdp_get_mdata();



	if (!ctl || !split_ctl || !mdata)

		return -ENODEV;



	/* setup split ctl mixer as right mixer of original ctl so that

	 * original ctl can work the same way as dual pipe solution */

	ctl->mixer_right = split_ctl->mixer_left;



	if ((mdata->mdp_rev >= MDSS_MDP_HW_REV_103) &&

		(ctl->opmode == MDSS_MDP_CTL_OP_VIDEO_MODE))

		ctl->split_flush_en = true;



	return 0;

}
@@ -1035,7 +1041,7 @@ static void mdss_mdp_ctl_split_display_enable(int enable, 
	MDSS_MDP_REG_WRITE(MDSS_MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTRL, lower);

	MDSS_MDP_REG_WRITE(MDSS_MDP_REG_SPLIT_DISPLAY_EN, enable);



	if (main_ctl->mdata->mdp_rev >= MDSS_MDP_HW_REV_103)

	if (main_ctl->split_flush_en)

		MDSS_MDP_REG_WRITE(MMSS_MDP_MDP_SSPP_SPARE_0,

			enable ? 0x1 : 0x0);

}
@@ -1941,7 +1947,7 @@ int mdss_mdp_display_commit(struct mdss_mdp_ctl *ctl, void *arg) 
		/* postprocessing setup, including dspp */

		mdss_mdp_pp_setup_locked(ctl);



	if (sctl && ctl->mdata->mdp_rev >= MDSS_MDP_HW_REV_103) {

	if (sctl && ctl->split_flush_en) {

		ctl->flush_bits |= sctl->flush_bits;

		sctl->flush_bits = 0;

	}