Loading drivers/gpu/msm/a4xx_reg.h +3 −0 Original line number Diff line number Diff line Loading @@ -83,6 +83,7 @@ enum a4xx_rb_perfctr_rb_sel { #define A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x2f #define A4XX_RBBM_INT_CLEAR_CMD 0x36 #define A4XX_RBBM_INT_0_MASK 0x37 #define A4XX_RBBM_ALWAYSON_COUNTER_CNTL 0x3d #define A4XX_RBBM_RBBM_CTL 0x3e #define A4XX_RBBM_CLOCK_CTL2 0x42 #define A4XX_RBBM_BLOCK_SW_RESET_CMD 0x45 Loading Loading @@ -387,6 +388,8 @@ enum a4xx_rb_perfctr_rb_sel { #define A4XX_RBBM_PERFCTR_PWR_0_HI 0x167 #define A4XX_RBBM_PERFCTR_PWR_1_LO 0x168 #define A4XX_RBBM_PERFCTR_PWR_1_HI 0x169 #define A4XX_RBBM_ALWAYSON_COUNTER_LO 0x16e #define A4XX_RBBM_ALWAYSON_COUNTER_HI 0x16f #define A4XX_RBBM_PERFCTR_CTL 0x170 #define A4XX_RBBM_PERFCTR_LOAD_CMD0 0x171 #define A4XX_RBBM_PERFCTR_LOAD_CMD1 0x172 Loading drivers/gpu/msm/adreno_a4xx.c +10 −0 Original line number Diff line number Diff line Loading @@ -713,6 +713,16 @@ uint64_t a4xx_perfcounter_read_vbif_pwr(struct adreno_device *adreno_dev, .regs[counter].value; } uint64_t a4xx_alwayson_counter_read(struct adreno_device *adreno_dev) { unsigned int lo, hi; kgsl_regread(&adreno_dev->dev, A4XX_RBBM_ALWAYSON_COUNTER_LO, &lo); kgsl_regread(&adreno_dev->dev, A4XX_RBBM_ALWAYSON_COUNTER_HI, &hi); return (((uint64_t) hi) << 32) | lo; } static void a4xx_err_callback(struct adreno_device *adreno_dev, int bit) { struct kgsl_device *device = &adreno_dev->dev; Loading drivers/gpu/msm/adreno_a4xx.h +2 −0 Original line number Diff line number Diff line Loading @@ -33,6 +33,8 @@ void a4xx_perfcounter_disable_vbif_pwr(struct adreno_device *adreno_dev, uint64_t a4xx_perfcounter_read_vbif_pwr(struct adreno_device *adreno_dev, unsigned int counter); uint64_t a4xx_alwayson_counter_read(struct adreno_device *adreno_dev); void a4xx_snapshot(struct adreno_device *adreno_dev, struct kgsl_snapshot *snapshot); Loading Loading
drivers/gpu/msm/a4xx_reg.h +3 −0 Original line number Diff line number Diff line Loading @@ -83,6 +83,7 @@ enum a4xx_rb_perfctr_rb_sel { #define A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x2f #define A4XX_RBBM_INT_CLEAR_CMD 0x36 #define A4XX_RBBM_INT_0_MASK 0x37 #define A4XX_RBBM_ALWAYSON_COUNTER_CNTL 0x3d #define A4XX_RBBM_RBBM_CTL 0x3e #define A4XX_RBBM_CLOCK_CTL2 0x42 #define A4XX_RBBM_BLOCK_SW_RESET_CMD 0x45 Loading Loading @@ -387,6 +388,8 @@ enum a4xx_rb_perfctr_rb_sel { #define A4XX_RBBM_PERFCTR_PWR_0_HI 0x167 #define A4XX_RBBM_PERFCTR_PWR_1_LO 0x168 #define A4XX_RBBM_PERFCTR_PWR_1_HI 0x169 #define A4XX_RBBM_ALWAYSON_COUNTER_LO 0x16e #define A4XX_RBBM_ALWAYSON_COUNTER_HI 0x16f #define A4XX_RBBM_PERFCTR_CTL 0x170 #define A4XX_RBBM_PERFCTR_LOAD_CMD0 0x171 #define A4XX_RBBM_PERFCTR_LOAD_CMD1 0x172 Loading
drivers/gpu/msm/adreno_a4xx.c +10 −0 Original line number Diff line number Diff line Loading @@ -713,6 +713,16 @@ uint64_t a4xx_perfcounter_read_vbif_pwr(struct adreno_device *adreno_dev, .regs[counter].value; } uint64_t a4xx_alwayson_counter_read(struct adreno_device *adreno_dev) { unsigned int lo, hi; kgsl_regread(&adreno_dev->dev, A4XX_RBBM_ALWAYSON_COUNTER_LO, &lo); kgsl_regread(&adreno_dev->dev, A4XX_RBBM_ALWAYSON_COUNTER_HI, &hi); return (((uint64_t) hi) << 32) | lo; } static void a4xx_err_callback(struct adreno_device *adreno_dev, int bit) { struct kgsl_device *device = &adreno_dev->dev; Loading
drivers/gpu/msm/adreno_a4xx.h +2 −0 Original line number Diff line number Diff line Loading @@ -33,6 +33,8 @@ void a4xx_perfcounter_disable_vbif_pwr(struct adreno_device *adreno_dev, uint64_t a4xx_perfcounter_read_vbif_pwr(struct adreno_device *adreno_dev, unsigned int counter); uint64_t a4xx_alwayson_counter_read(struct adreno_device *adreno_dev); void a4xx_snapshot(struct adreno_device *adreno_dev, struct kgsl_snapshot *snapshot); Loading