Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2ab3f29d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'akpm' (Andrew's fixes) 

Merge misc fixes from Andrew Morton:
 "18 total.  15 fixes and some updates to a device_cgroup patchset which
  bring it up to date with the version which I should have merged in the
  first place."

* emailed patches from Andrew Morton <akpm@linux-foundation.org>: (18 patches)
  fs/compat_ioctl.c: VIDEO_SET_SPU_PALETTE missing error check
  gen_init_cpio: avoid stack overflow when expanding
  drivers/rtc/rtc-imxdi.c: add missing spin lock initialization
  mm, numa: avoid setting zone_reclaim_mode unless a node is sufficiently distant
  pidns: limit the nesting depth of pid namespaces
  drivers/dma/dw_dmac: make driver's endianness configurable
  mm/mmu_notifier: allocate mmu_notifier in advance
  tools/testing/selftests/epoll/test_epoll.c: fix build
  UAPI: fix tools/vm/page-types.c
  mm/page_alloc.c:alloc_contig_range(): return early for err path
  rbtree: include linux/compiler.h for definition of __always_inline
  genalloc: stop crashing the system when destroying a pool
  backlight: ili9320: add missing SPI dependency
  device_cgroup: add proper checking when changing default behavior
  device_cgroup: stop using simple_strtoul()
  device_cgroup: rename deny_all to behavior
  cgroup: fix invalid rcu dereference
  mm: fix XFS oops due to dirty pages without buffers on s390
parents b1e4279e 12176503

drivers/dma/Kconfig

+11 −0
Original line number Original line Diff line number Diff line
@@ -90,6 +90,17 @@ config DW_DMAC 
	  Support the Synopsys DesignWare AHB DMA controller.  This

	  Support the Synopsys DesignWare AHB DMA controller.  This

	  can be integrated in chips such as the Atmel AT32ap7000.

	  can be integrated in chips such as the Atmel AT32ap7000.





config DW_DMAC_BIG_ENDIAN_IO

	bool "Use big endian I/O register access"

	default y if AVR32

	depends on DW_DMAC

	help

	  Say yes here to use big endian I/O access when reading and writing

	  to the DMA controller registers. This is needed on some platforms,

	  like the Atmel AVR32 architecture.



	  If unsure, use the default setting.



config AT_HDMAC

config AT_HDMAC

	tristate "Atmel AHB DMA support"

	tristate "Atmel AHB DMA support"

	depends on ARCH_AT91

	depends on ARCH_AT91

drivers/dma/dw_dmac_regs.h

+13 −5
Original line number Original line Diff line number Diff line
@@ -98,9 +98,17 @@ struct dw_dma_regs { 
	u32	DW_PARAMS;

	u32	DW_PARAMS;

};

};





#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO

#define dma_readl_native ioread32be

#define dma_writel_native iowrite32be

#else

#define dma_readl_native readl

#define dma_writel_native writel

#endif



/* To access the registers in early stage of probe */

/* To access the registers in early stage of probe */

#define dma_read_byaddr(addr, name) \

#define dma_read_byaddr(addr, name) \

	readl((addr) + offsetof(struct dw_dma_regs, name))

	dma_readl_native((addr) + offsetof(struct dw_dma_regs, name))





/* Bitfields in DW_PARAMS */

/* Bitfields in DW_PARAMS */

#define DW_PARAMS_NR_CHAN	8		/* number of channels */

#define DW_PARAMS_NR_CHAN	8		/* number of channels */
@@ -216,9 +224,9 @@ __dwc_regs(struct dw_dma_chan *dwc) 
}

}





#define channel_readl(dwc, name) \

#define channel_readl(dwc, name) \

	readl(&(__dwc_regs(dwc)->name))

	dma_readl_native(&(__dwc_regs(dwc)->name))

#define channel_writel(dwc, name, val) \

#define channel_writel(dwc, name, val) \

	writel((val), &(__dwc_regs(dwc)->name))

	dma_writel_native((val), &(__dwc_regs(dwc)->name))





static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)

static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)

{

{
@@ -246,9 +254,9 @@ static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw) 
}

}





#define dma_readl(dw, name) \

#define dma_readl(dw, name) \

	readl(&(__dw_regs(dw)->name))

	dma_readl_native(&(__dw_regs(dw)->name))

#define dma_writel(dw, name, val) \

#define dma_writel(dw, name, val) \

	writel((val), &(__dw_regs(dw)->name))

	dma_writel_native((val), &(__dw_regs(dw)->name))





#define channel_set_bit(dw, reg, mask) \

#define channel_set_bit(dw, reg, mask) \

	dma_writel(dw, reg, ((mask) << 8) | (mask))

	dma_writel(dw, reg, ((mask) << 8) | (mask))

drivers/rtc/rtc-imxdi.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -392,6 +392,8 @@ static int dryice_rtc_probe(struct platform_device *pdev) 
	if (imxdi->ioaddr == NULL)

	if (imxdi->ioaddr == NULL)

		return -ENOMEM;

		return -ENOMEM;





	spin_lock_init(&imxdi->irq_lock);



	imxdi->irq = platform_get_irq(pdev, 0);

	imxdi->irq = platform_get_irq(pdev, 0);

	if (imxdi->irq < 0)

	if (imxdi->irq < 0)

		return imxdi->irq;

		return imxdi->irq;

drivers/video/backlight/Kconfig

+2 −1
Original line number Original line Diff line number Diff line
@@ -60,7 +60,8 @@ config LCD_LTV350QV 
	  The LTV350QV panel is present on all ATSTK1000 boards.

	  The LTV350QV panel is present on all ATSTK1000 boards.





config LCD_ILI9320

config LCD_ILI9320

	tristate

	tristate "ILI Technology ILI9320 controller support"

	depends on SPI

	help

	help

	  If you have a panel based on the ILI9320 controller chip

	  If you have a panel based on the ILI9320 controller chip

	  then say y to include a power driver for it.

	  then say y to include a power driver for it.

fs/compat_ioctl.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -210,6 +210,8 @@ static int do_video_set_spu_palette(unsigned int fd, unsigned int cmd, 




	err  = get_user(palp, &up->palette);

	err  = get_user(palp, &up->palette);

	err |= get_user(length, &up->length);

	err |= get_user(length, &up->length);

	if (err)

		return -EFAULT;





	up_native = compat_alloc_user_space(sizeof(struct video_spu_palette));

	up_native = compat_alloc_user_space(sizeof(struct video_spu_palette));

	err  = put_user(compat_ptr(palp), &up_native->palette);

	err  = put_user(compat_ptr(palp), &up_native->palette);