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Commit 1dccd165 authored by Vignesh Radhakrishnan's avatar Vignesh Radhakrishnan
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ARM: dts: msm: fix etr byte counter interrupt for 8092 



Modify CoreSight ETR byte counter interrupt number
to the correct value for 8092.

Change-Id: I333fa026b2989d5dbcfec14032a18324aad08a42
Signed-off-by: default avatarVignesh Radhakrishnan <vigneshr@codeaurora.org>
parent e36b0ea5

arch/arm/boot/dts/qti/mpq8092-coresight.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@ 
		reg = <0xfc326000 0x1000>,

		      <0xfc37c000 0x3000>;

		reg-names = "tmc-base", "bam-base";

		interrupts = <0 270 0>;

		interrupts = <0 166 0>;

		interrupt-names = "byte-cntr-irq";



		qcom,memory-size = <0x100000>;