Commit 12be609b authored Mar 11, 2015 by Russ W. Knize Committed by Dyneteve May 02, 2018

clk: gcc-8916: add 160Mhz and 177MHz to SDCC tables



Add a 177.77MHz to the SDC2 clock table to avoid the problematic
200MHz clock jitter problem.  Also add 160MHz to both SDC1 and SDC2.

Change-Id: Icdb39997fa42423ec091a43f148971541eec9cd5
Signed-off-by: Russ Knize <Russ.Knize@motorola.com>
Reviewed-on: http://gerrit.mot.com/721794


SLTApproved: Slta Waiver <sltawvr@motorola.com>
Tested-by: Jira Key <jirakey@motorola.com>
Reviewed-by: Igor Kovalenko <igork@motorola.com>
Submit-Approved: Jira Key <jirakey@motorola.com>

parent 77aa22b8

drivers/clk/qcom/clock-gcc-8916.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -1193,6 +1193,7 @@ static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
		F( 25000000, gpll0, 16, 1, 2),
		F( 50000000, gpll0, 16, 0, 0),
		F( 100000000, gpll0, 8, 0, 0),
		F( 160000000, gpll0, 5, 0, 0),
		F( 177770000, gpll0, 4.5, 0, 0),
		F_END
		};
		@@ -1218,6 +1219,7 @@ static struct clk_freq_tbl ftbl_gcc_sdcc2_apps_clk[] = {
		F( 25000000, gpll0, 16, 1, 2),
		F( 50000000, gpll0, 16, 0, 0),
		F( 100000000, gpll0, 8, 0, 0),
		F( 160000000, gpll0, 5, 0, 0),
		F( 177770000, gpll0, 4.5, 0, 0),
		F( 200000000, gpll0, 4, 0, 0),
		F_END