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Commit 0f23201b authored by minz1's avatar minz1
Browse files

Merge tag 'v3.10.85' into cm-14.1 

This is the 3.10.85 stable release
parents aed5aa6b b7c42895

Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt

+2 −2
Original line number Diff line number Diff line
@@ -91,5 +91,5 @@ mpp61 61 gpo, dev(wen1), uart1(txd), audio(rclk) 
mpp62         62       gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),

                       audio(mclk), uart0(cts)

mpp63         63       gpo, spi0(sck), tclk

mpp64         64       gpio, spi0(miso), spi0-1(cs1)

mpp65         65       gpio, spi0(mosi), spi0-1(cs2)
 
mpp64         64       gpio, spi0(miso), spi0(cs1)

mpp65         65       gpio, spi0(mosi), spi0(cs2)

Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt

+13 −19
Original line number Diff line number Diff line
@@ -41,15 +41,15 @@ mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk) 
mpp21         21       gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat)

mpp22         22       gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)

mpp23         23       gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)

mpp24         24       gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst)

mpp25         25       gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk)

mpp26         26       gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)

mpp24         24       gpio, lcd(hsync), sata1(prsnt), tdm(rst)

mpp25         25       gpio, lcd(vsync), sata0(prsnt), tdm(pclk)

mpp26         26       gpio, lcd(clk), tdm(fsync)

mpp27         27       gpio, lcd(e), tdm(dtx), ptp(trig)

mpp28         28       gpio, lcd(pwm), tdm(drx), ptp(evreq)

mpp29         29       gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)

mpp29         29       gpio, lcd(ref-clk), tdm(int0), ptp(clk)

mpp30         30       gpio, tdm(int1), sd0(clk)

mpp31         31       gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)

mpp32         32       gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)

mpp31         31       gpio, tdm(int2), sd0(cmd)

mpp32         32       gpio, tdm(int3), sd0(d0)

mpp33         33       gpio, tdm(int4), sd0(d1), mem(bat)

mpp34         34       gpio, tdm(int5), sd0(d2), sata0(prsnt)

mpp35         35       gpio, tdm(int6), sd0(d3), sata1(prsnt)
@@ -57,21 +57,18 @@ mpp36 36 gpio, spi(mosi) 
mpp37         37       gpio, spi(miso)

mpp38         38       gpio, spi(sck)

mpp39         39       gpio, spi(cs0)

mpp40         40       gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),

                       pcie(clkreq0)

mpp40         40       gpio, spi(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0)

mpp41         41       gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),

                       pcie(clkreq1)

mpp42         42       gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),

                       vdd(cpu0-pd)

mpp43         43       gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),

                       vdd(cpu2-3-pd){1}

mpp42         42       gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer)

mpp43         43       gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout)

mpp44         44       gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),

                       mem(bat)

mpp45         45       gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)

mpp46         46       gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt)

mpp47         47       gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),

                       ref(clkout)

mpp48         48       gpio, tclk, dev(burst/last)

mpp48         48       gpio, dev(clkout), dev(burst/last)



* Marvell Armada XP (mv78260 and mv78460 only)
@@ -83,9 +80,9 @@ mpp51 51 gpio, dev(ad16) 
mpp52         52       gpio, dev(ad17)

mpp53         53       gpio, dev(ad18)

mpp54         54       gpio, dev(ad19)

mpp55         55       gpio, dev(ad20), vdd(cpu0-pd)

mpp56         56       gpio, dev(ad21), vdd(cpu1-pd)

mpp57         57       gpio, dev(ad22), vdd(cpu2-3-pd){1}

mpp55         55       gpio, dev(ad20)

mpp56         56       gpio, dev(ad21)

mpp57         57       gpio, dev(ad22)

mpp58         58       gpio, dev(ad23)

mpp59         59       gpio, dev(ad24)

mpp60         60       gpio, dev(ad25)
@@ -95,6 +92,3 @@ mpp63 63 gpio, dev(ad28) 
mpp64         64       gpio, dev(ad29)

mpp65         65       gpio, dev(ad30)

mpp66         66       gpio, dev(ad31)
 


Notes:

* {1} vdd(cpu2-3-pd) only available on mv78460.

Documentation/devicetree/bindings/spi/spi_pl022.txt

+1 −1
Original line number Diff line number Diff line
@@ -4,9 +4,9 @@ Required properties: 
- compatible : "arm,pl022", "arm,primecell"

- reg : Offset and length of the register set for the device

- interrupts : Should contain SPI controller interrupt

- num-cs : total number of chipselects



Optional properties:

- num-cs : total number of chipselects

- cs-gpios : should specify GPIOs used for chipselects.

  The gpios will be referred to as reg = <index> in the SPI child nodes.

  If unspecified, a single SPI device without a chip select can be used.

Makefile

+1 −1
Original line number Diff line number Diff line 
VERSION = 3

PATCHLEVEL = 10

SUBLEVEL = 84

SUBLEVEL = 85

EXTRAVERSION =

NAME = TOSSUG Baby Fish

arch/arc/include/asm/cmpxchg.h

+5 −4
Original line number Diff line number Diff line
@@ -25,10 +25,11 @@ __cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new) 
	"	scond   %3, [%1]	\n"

	"	bnz     1b		\n"

	"2:				\n"

	: "=&r"(prev)

	: "r"(ptr), "ir"(expected),

	  "r"(new) /* can't be "ir". scond can't take limm for "b" */

	: "cc");

	: "=&r"(prev)	/* Early clobber, to prevent reg reuse */

	: "r"(ptr),	/* Not "m": llock only supports reg direct addr mode */

	  "ir"(expected),

	  "r"(new)	/* can't be "ir". scond can't take LIMM for "b" */

	: "cc", "memory"); /* so that gcc knows memory is being written here */



	return prev;

}