Loading arch/arm/mach-msm/clock-9630.c +2 −0 Original line number Original line Diff line number Diff line Loading @@ -1330,6 +1330,7 @@ static struct branch_clk gcc_pcie_pipe_clk = { .bcr_reg = PCIEPHY_PHY_BCR, .bcr_reg = PCIEPHY_PHY_BCR, .has_sibling = 0, .has_sibling = 0, .base = &virt_bases[GCC_BASE], .base = &virt_bases[GCC_BASE], .halt_check = DELAY, .c = { .c = { .dbg_name = "gcc_pcie_pipe_clk", .dbg_name = "gcc_pcie_pipe_clk", .parent = &pcie_pipe_clk_src.c, .parent = &pcie_pipe_clk_src.c, Loading Loading @@ -1494,6 +1495,7 @@ static struct branch_clk gcc_usb3_pipe_clk = { .bcr_reg = USB3PHY_PHY_BCR, .bcr_reg = USB3PHY_PHY_BCR, .has_sibling = 0, .has_sibling = 0, .base = &virt_bases[GCC_BASE], .base = &virt_bases[GCC_BASE], .halt_check = DELAY, .c = { .c = { .dbg_name = "gcc_usb3_pipe_clk", .dbg_name = "gcc_usb3_pipe_clk", .parent = &usb3_pipe_clk_src.c, .parent = &usb3_pipe_clk_src.c, Loading Loading
arch/arm/mach-msm/clock-9630.c +2 −0 Original line number Original line Diff line number Diff line Loading @@ -1330,6 +1330,7 @@ static struct branch_clk gcc_pcie_pipe_clk = { .bcr_reg = PCIEPHY_PHY_BCR, .bcr_reg = PCIEPHY_PHY_BCR, .has_sibling = 0, .has_sibling = 0, .base = &virt_bases[GCC_BASE], .base = &virt_bases[GCC_BASE], .halt_check = DELAY, .c = { .c = { .dbg_name = "gcc_pcie_pipe_clk", .dbg_name = "gcc_pcie_pipe_clk", .parent = &pcie_pipe_clk_src.c, .parent = &pcie_pipe_clk_src.c, Loading Loading @@ -1494,6 +1495,7 @@ static struct branch_clk gcc_usb3_pipe_clk = { .bcr_reg = USB3PHY_PHY_BCR, .bcr_reg = USB3PHY_PHY_BCR, .has_sibling = 0, .has_sibling = 0, .base = &virt_bases[GCC_BASE], .base = &virt_bases[GCC_BASE], .halt_check = DELAY, .c = { .c = { .dbg_name = "gcc_usb3_pipe_clk", .dbg_name = "gcc_usb3_pipe_clk", .parent = &usb3_pipe_clk_src.c, .parent = &usb3_pipe_clk_src.c, Loading