Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 032938f8 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
Browse files

Merge "msm: kgsl: Update pagetable using indirect buffer"

parents 83cb3d64 dcb37eee

drivers/gpu/msm/a3xx_reg.h

+3 −2
Original line number Diff line number Diff line
@@ -207,6 +207,7 @@ 
#define A3XX_CP_SCRATCH_ADDR 0x01DD

#define A3XX_CP_STATE_DEBUG_INDEX 0x01EC

#define A3XX_CP_STATE_DEBUG_DATA 0x01ED

#define A3XX_CP_CNTL 0x01F4

#define A3XX_CP_WFI_PEND_CTR 0x01F5

#define A3XX_CP_ME_CNTL 0x01F6

#define A3XX_CP_ME_STATUS 0x01F7
@@ -245,8 +246,8 @@ 
#define A3XX_CP_PROTECT_REG_F 0x46F

#define A3XX_CP_STAT 0x047F

#define A3XX_CP_SCRATCH_REG0 0x578

#define A3XX_CP_SCRATCH_REG2 0x57A

#define A3XX_CP_SCRATCH_REG3 0x57B

#define A3XX_CP_SCRATCH_REG6 0x57E

#define A3XX_CP_SCRATCH_REG7 0x57F

#define A3XX_VSC_BIN_SIZE 0xC01

#define A3XX_VSC_SIZE_ADDRESS 0xC02

#define A3XX_VSC_PIPE_CONFIG_0 0xC06

drivers/gpu/msm/a4xx_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -476,6 +476,7 @@ enum a4xx_rb_perfctr_rb_sel { 
#define A4XX_CP_PROTECT_CTRL		0x250

#define A4XX_CP_SCRATCH_UMASK		0x228

#define A4XX_CP_SCRATCH_ADDR		0x229

#define A4XX_CP_CNTL			0x22c

#define A4XX_CP_ME_CNTL			0x22d

#define A4XX_CP_STATE_DEBUG_INDEX	0x22F

#define A4XX_CP_STATE_DEBUG_DATA	0x230
@@ -494,6 +495,8 @@ enum a4xx_rb_perfctr_rb_sel { 
#define A4XX_CP_PERFCTR_CP_SEL_7	0x507



#define A4XX_CP_SCRATCH_REG0		0x578

#define A4XX_CP_SCRATCH_REG6		0x57e

#define A4XX_CP_SCRATCH_REG7		0x57f



/* SP registers */

#define A4XX_SP_VS_OBJ_START		0x22e1

drivers/gpu/msm/adreno.c

+9 −0
Original line number Diff line number Diff line
@@ -1548,6 +1548,7 @@ static int adreno_stop(struct kgsl_device *device) 
 */

int adreno_reset(struct kgsl_device *device)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	int ret = -EINVAL;

	struct kgsl_mmu *mmu = &device->mmu;

	int i = 0;
@@ -1587,6 +1588,10 @@ int adreno_reset(struct kgsl_device *device) 


	/* Set the page table back to the default page table */

	kgsl_mmu_set_pt(&device->mmu, device->mmu.defaultpagetable);

	kgsl_sharedmem_writel(device,

		&adreno_dev->ringbuffers[0].pagetable_desc,

		offsetof(struct adreno_ringbuffer_pagetable_info,

			current_global_ptname), 0);



	return ret;

}
@@ -2641,6 +2646,10 @@ static int adreno_suspend_context(struct kgsl_device *device) 
		return status;

	/* set the device to default pagetable */

	kgsl_mmu_set_pt(&device->mmu, device->mmu.defaultpagetable);

	kgsl_sharedmem_writel(device,

		&adreno_dev->ringbuffers[0].pagetable_desc,

		offsetof(struct adreno_ringbuffer_pagetable_info,

			current_global_ptname), 0);

	/* set ringbuffers to NULL ctxt */

	adreno_set_active_ctx_null(adreno_dev);

drivers/gpu/msm/adreno.h

+43 −2
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#define __ADRENO_H



#include "kgsl_device.h"

#include "kgsl_sharedmem.h"

#include "adreno_drawctxt.h"

#include "adreno_ringbuffer.h"

#include "adreno_profile.h"
@@ -78,6 +79,8 @@ 
#define ADRENO_SPTP_PC BIT(5)

/* The core supports Peak Power Detection(PPD)*/

#define ADRENO_PPD BIT(6)

/* The microcode supports register to register copy and compare */

#define ADRENO_HAS_REG_TO_REG_CMDS BIT(7)



/* Flags to control command packet settings */

#define KGSL_CMD_FLAGS_NONE             0
@@ -391,12 +394,16 @@ enum adreno_regs { 
	ADRENO_REG_CP_RB_BASE,

	ADRENO_REG_CP_RB_RPTR,

	ADRENO_REG_CP_RB_WPTR,

	ADRENO_REG_CP_CNTL,

	ADRENO_REG_CP_ME_CNTL,

	ADRENO_REG_CP_RB_CNTL,

	ADRENO_REG_CP_IB1_BASE,

	ADRENO_REG_CP_IB1_BUFSZ,

	ADRENO_REG_CP_IB2_BASE,

	ADRENO_REG_CP_IB2_BUFSZ,

	ADRENO_REG_CP_TIMESTAMP,

	ADRENO_REG_CP_SCRATCH_REG6,

	ADRENO_REG_CP_SCRATCH_REG7,

	ADRENO_REG_CP_ME_RAM_RADDR,

	ADRENO_REG_CP_ROQ_ADDR,

	ADRENO_REG_CP_ROQ_DATA,
@@ -407,7 +414,6 @@ enum adreno_regs { 
	ADRENO_REG_CP_MEQ_DATA,

	ADRENO_REG_CP_HW_FAULT,

	ADRENO_REG_CP_PROTECT_STATUS,

	ADRENO_REG_SCRATCH_REG2,

	ADRENO_REG_RBBM_STATUS,

	ADRENO_REG_RBBM_PERFCTR_CTL,

	ADRENO_REG_RBBM_PERFCTR_LOAD_CMD0,
@@ -779,6 +785,9 @@ int adreno_rb_readtimestamp(struct kgsl_device *device, 
int adreno_iommu_set_pt(struct adreno_ringbuffer *rb,

			struct kgsl_pagetable *new_pt);



void adreno_iommu_set_pt_generate_rb_cmds(struct adreno_ringbuffer *rb,

					struct kgsl_pagetable *pt);



static inline int adreno_is_a3xx(struct adreno_device *adreno_dev)

{

	return ((ADRENO_GPUREV(adreno_dev) >= 300) &&
@@ -878,7 +887,9 @@ static inline int __adreno_add_idle_indirect_cmds(unsigned int *cmds, 
	 * the commands in indirect buffer have completed. We need to stall

	 * prefetch with a nop indirect buffer when updating pagetables

	 * because it provides stabler synchronization */

	*cmds++ = CP_HDR_INDIRECT_BUFFER_PFD;

	*cmds++ = cp_type3_packet(CP_WAIT_FOR_ME, 1);

	*cmds++ = 0;

	*cmds++ = CP_HDR_INDIRECT_BUFFER_PFE;

	*cmds++ = nop_gpuaddr;

	*cmds++ = 2;

	*cmds++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);
@@ -1327,6 +1338,9 @@ static inline void adreno_set_active_ctx_null(struct adreno_device *adreno_dev) 
		if (rb->drawctxt_active)

			kgsl_context_put(&(rb->drawctxt_active->base));

		rb->drawctxt_active = NULL;

		kgsl_sharedmem_writel(rb->device, &rb->pagetable_desc,

			offsetof(struct adreno_ringbuffer_pagetable_info,

				current_rb_ptname), 0);

	}

}
@@ -1350,4 +1364,31 @@ static inline bool adreno_use_cpu_path(struct adreno_device *adreno_dev) 
		adreno_dev->dev.cff_dump_enable);

}



/**

 * adreno_set_apriv() - Generate commands to set/reset the APRIV

 * @adreno_dev: Device on which the commands will execute

 * @cmds: The memory pointer where commands are generated

 * @set: If set then APRIV is set else reset

 *

 * Returns the number of commands generated

 */

static inline unsigned int adreno_set_apriv(struct adreno_device *adreno_dev,

				unsigned int *cmds, int set)

{

	unsigned int *cmds_orig = cmds;



	*cmds++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);

	*cmds++ = 0;

	*cmds++ = cp_type3_packet(CP_WAIT_FOR_ME, 1);

	*cmds++ = 0;

	*cmds++ = cp_type0_packet(adreno_getreg(adreno_dev,

				ADRENO_REG_CP_CNTL), 1);

	if (set)

		*cmds++ = 1;

	else

		*cmds++ = 0;



	return cmds - cmds_orig;

}



#endif /*__ADRENO_H */

drivers/gpu/msm/adreno_a3xx.c

+6 −2
Original line number Diff line number Diff line
@@ -247,7 +247,8 @@ int adreno_a3xx_pwron_fixup_init(struct adreno_device *adreno_dev) 
		return 0;



	ret = kgsl_allocate_global(&adreno_dev->dev,

		&adreno_dev->pwron_fixup, PAGE_SIZE, KGSL_MEMFLAGS_GPUREADONLY);

		&adreno_dev->pwron_fixup, PAGE_SIZE,

		KGSL_MEMFLAGS_GPUREADONLY, 0);



	if (ret)

		return ret;
@@ -2402,12 +2403,16 @@ static unsigned int a3xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_BASE, A3XX_CP_RB_BASE),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_RPTR, A3XX_CP_RB_RPTR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_WPTR, A3XX_CP_RB_WPTR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_CNTL, A3XX_CP_CNTL),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_ME_CNTL, A3XX_CP_ME_CNTL),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_CNTL, A3XX_CP_RB_CNTL),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_IB1_BASE, A3XX_CP_IB1_BASE),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_IB1_BUFSZ, A3XX_CP_IB1_BUFSZ),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_IB2_BASE, A3XX_CP_IB2_BASE),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_IB2_BUFSZ, A3XX_CP_IB2_BUFSZ),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_TIMESTAMP, A3XX_CP_SCRATCH_REG0),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_SCRATCH_REG6, A3XX_CP_SCRATCH_REG6),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_SCRATCH_REG7, A3XX_CP_SCRATCH_REG7),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_ME_RAM_RADDR, A3XX_CP_ME_RAM_RADDR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_ROQ_ADDR, A4XX_CP_ROQ_ADDR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_ROQ_DATA, A3XX_CP_ROQ_DATA),
@@ -2440,7 +2445,6 @@ static unsigned int a3xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
				A3XX_VPC_VPC_DEBUG_RAM_READ),

	ADRENO_REG_DEFINE(ADRENO_REG_PA_SC_AA_CONFIG, A3XX_PA_SC_AA_CONFIG),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PM_OVERRIDE2, A3XX_RBBM_PM_OVERRIDE2),

	ADRENO_REG_DEFINE(ADRENO_REG_SCRATCH_REG2, A3XX_CP_SCRATCH_REG2),

	ADRENO_REG_DEFINE(ADRENO_REG_SQ_GPR_MANAGEMENT, A3XX_SQ_GPR_MANAGEMENT),

	ADRENO_REG_DEFINE(ADRENO_REG_SQ_INST_STORE_MANAGMENT,

				A3XX_SQ_INST_STORE_MANAGMENT),