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Commit 01953e5b authored by Phani Kumar Uppalapati's avatar Phani Kumar Uppalapati
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ASoC: wcd9306: Update DEM-2 mux input based on codec type 



Tapan codec has two variants wcd9306 and wcd9302.
WCD9302 codec does not have compander block and hence
the DEM-2 mux input should always be selected to NZ_SHAPER.
Selecting the mux to CLASS_H_BUFFER would cause audio mute
if the CP clock is not enabled, which is the case when RX2
interpolator path is shared for HPHR and LO.

Change-Id: I7ea00a30d0554cc9e012fd0975c9a28e7cdf12f0
Signed-off-by: default avatarPhani Kumar Uppalapati <phaniu@codeaurora.org>
parent 6791a1be

sound/soc/codecs/wcd9306.c

+28 −3
Original line number Diff line number Diff line
@@ -2562,6 +2562,29 @@ static int tapan_codec_enable_vdd_spkr(struct snd_soc_dapm_widget *w, 
	return 0;

}



static int tapan_codec_rx_dem_select(struct snd_soc_dapm_widget *w,

			struct snd_kcontrol *kcontrol, int event)

{



	struct snd_soc_codec *codec = w->codec;



	pr_debug("%s %d %s\n", __func__, event, w->name);

	switch (event) {

	case SND_SOC_DAPM_PRE_PMU:

		if (codec_ver == WCD9306)

			snd_soc_update_bits(codec, TAPAN_A_CDC_RX2_B6_CTL,

					    1 << 5, 1 << 5);

		break;

	case SND_SOC_DAPM_POST_PMD:

		if (codec_ver == WCD9306)

			snd_soc_update_bits(codec, TAPAN_A_CDC_RX2_B6_CTL,

					    1 << 5, 0);

		break;

	}



	return 0;

}



static int tapan_codec_enable_interpolator(struct snd_soc_dapm_widget *w,

	struct snd_kcontrol *kcontrol, int event)

{
@@ -4600,8 +4623,10 @@ static const struct snd_soc_dapm_widget tapan_common_dapm_widgets[] = { 


	SND_SOC_DAPM_MIXER("RX1 CHAIN", TAPAN_A_CDC_RX1_B6_CTL, 5, 0,

						NULL, 0),

	SND_SOC_DAPM_MIXER("RX2 CHAIN", TAPAN_A_CDC_RX2_B6_CTL, 5, 0,

						NULL, 0),



	SND_SOC_DAPM_MIXER_E("RX2 CHAIN", SND_SOC_NOPM, 0, 0, NULL,

		0, tapan_codec_rx_dem_select, SND_SOC_DAPM_PRE_PMU |

		SND_SOC_DAPM_POST_PMD),



	SND_SOC_DAPM_MUX_E("CLASS_H_DSM MUX", SND_SOC_NOPM, 0, 0,

		&class_h_dsm_mux, tapan_codec_dsm_mux_event,
@@ -5107,7 +5132,7 @@ static const struct tapan_reg_mask_val tapan_reg_defaults[] = { 


	/* RX1 and RX2 defaults */

	TAPAN_REG_VAL(TAPAN_A_CDC_RX1_B6_CTL, 0xA0),

	TAPAN_REG_VAL(TAPAN_A_CDC_RX2_B6_CTL, 0xA0),

	TAPAN_REG_VAL(TAPAN_A_CDC_RX2_B6_CTL, 0x80),



	/* Heaset set Right from RX2 */

	TAPAN_REG_VAL(TAPAN_A_CDC_CONN_RX2_B2_CTL, 0x10),