Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 151b7599 authored by Axel Lin's avatar Axel Lin Committed by Mark Brown
Browse files

ASoC: wm8900: Fix wrong mask for setting DAC_CLKDIV/ADC_CLKDIV/LRCLK_MODE 



After checking the datasheet, I think what we want to do here is to
clear the WM8900_REG_CLOCKING2_DAC_CLKDIV/WM8900_REG_CLOCKING2_ADC_CLKDIV/
WM8900_REG_DACCTRL_AIF_LRCLKRATE bits and then OR with div value.

Signed-off-by: default avatarAxel Lin <axel.lin@gmail.com>
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent df3431b7

sound/soc/codecs/wm8900.c

+3 −3
Original line number Diff line number Diff line
@@ -844,17 +844,17 @@ static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai, 
	case WM8900_DAC_CLKDIV:

		reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);

		snd_soc_write(codec, WM8900_REG_CLOCKING2,

			     div | (reg & WM8900_REG_CLOCKING2_DAC_CLKDIV));

			     div | (reg & ~WM8900_REG_CLOCKING2_DAC_CLKDIV));

		break;

	case WM8900_ADC_CLKDIV:

		reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);

		snd_soc_write(codec, WM8900_REG_CLOCKING2,

			     div | (reg & WM8900_REG_CLOCKING2_ADC_CLKDIV));

			     div | (reg & ~WM8900_REG_CLOCKING2_ADC_CLKDIV));

		break;

	case WM8900_LRCLK_MODE:

		reg = snd_soc_read(codec, WM8900_REG_DACCTRL);

		snd_soc_write(codec, WM8900_REG_DACCTRL,

			     div | (reg & WM8900_REG_DACCTRL_AIF_LRCLKRATE));

			     div | (reg & ~WM8900_REG_DACCTRL_AIF_LRCLKRATE));

		break;

	default:

		return -EINVAL;