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Commit c3a9f435 authored by Mike Frysinger's avatar Mike Frysinger Committed by Bryan Wu
Browse files

Blackfin arch: cplb and map header file cleanup 



 - remove duplicated defines for the BF561
 - generalize L2 support (so that it works for BF54x) and mark it executable
 - add support for reading/executing the Boot ROM sections
   (since it has data/functions we may need at runtime)
 - and fixup names for each map

Signed-off-by: default avatarMike Frysinger <michael.frysinger@analog.com>
Signed-off-by: default avatarBryan Wu <bryan.wu@analog.com>
parent 81a487a5

arch/blackfin/kernel/cplbinit.c

+26 −16
Original line number Diff line number Diff line
@@ -64,7 +64,7 @@ static struct cplb_desc cplb_data[] = { 
#else

		.valid = 0,

#endif

		.name = "ZERO Pointer Saveguard",

		.name = "Zero Pointer Guard Page",

	},

	{

		.start = L1_CODE_START,
@@ -98,7 +98,7 @@ static struct cplb_desc cplb_data[] = { 
		.i_conf = SDRAM_IGENERIC,

		.d_conf = SDRAM_DGENERIC,

		.valid = 1,

		.name = "SDRAM Kernel",

		.name = "Kernel Memory",

	},

	{

		.start = 0, /* dynamic */
@@ -108,7 +108,7 @@ static struct cplb_desc cplb_data[] = { 
		.i_conf = SDRAM_IGENERIC,

		.d_conf = SDRAM_DNON_CHBL,

		.valid = 1,

		.name = "SDRAM RAM MTD",

		.name = "uClinux MTD Memory",

	},

	{

		.start = 0, /* dynamic */
@@ -117,7 +117,7 @@ static struct cplb_desc cplb_data[] = { 
		.attr = INITIAL_T | SWITCH_T | D_CPLB,

		.d_conf = SDRAM_DNON_CHBL,

		.valid = 1,

		.name = "SDRAM Uncached DMA ZONE",

		.name = "Uncached DMA Zone",

	},

	{

		.start = 0, /* dynamic */
@@ -127,7 +127,7 @@ static struct cplb_desc cplb_data[] = { 
		.i_conf = 0, /* dynamic */

		.d_conf = 0, /* dynamic */

		.valid = 1,

		.name = "SDRAM Reserved Memory",

		.name = "Reserved Memory",

	},

	{

		.start = ASYNC_BANK0_BASE,
@@ -136,14 +136,14 @@ static struct cplb_desc cplb_data[] = { 
		.attr = SWITCH_T | D_CPLB,

		.d_conf = SDRAM_EBIU,

		.valid = 1,

		.name = "ASYNC Memory",

		.name = "Asynchronous Memory Banks",

	},

	{

#if defined(CONFIG_BF561)

		.start = L2_SRAM,

		.end = L2_SRAM_END,

#ifdef L2_START

		.start = L2_START,

		.end = L2_START + L2_LENGTH,

		.psize = SIZE_1M,

		.attr = SWITCH_T | D_CPLB,

		.attr = SWITCH_T | I_CPLB | D_CPLB,

		.i_conf = L2_MEMORY,

		.d_conf = L2_MEMORY,

		.valid = 1,
@@ -151,7 +151,17 @@ static struct cplb_desc cplb_data[] = { 
		.valid = 0,

#endif

		.name = "L2 Memory",

	}

	},

	{

		.start = BOOT_ROM_START,

		.end = BOOT_ROM_START + BOOT_ROM_LENGTH,

		.psize = SIZE_1M,

		.attr = SWITCH_T | I_CPLB | D_CPLB,

		.i_conf = SDRAM_IGENERIC,

		.d_conf = SDRAM_DGENERIC,

		.valid = 1,

		.name = "On-Chip BootROM",

	},

};



static u16 __init lock_kernel_check(u32 start, u32 end)
@@ -343,7 +353,7 @@ void __init generate_cpl_tables(void) 
	else

		cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;



	for (i = ZERO_P; i <= L2_MEM; i++) {

	for (i = ZERO_P; i < ARRAY_SIZE(cplb_data); ++i) {

		if (!cplb_data[i].valid)

			continue;

include/asm-blackfin/mach-bf527/mem_map.h

+1 −0
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ 
/* Boot ROM Memory */



#define BOOT_ROM_START		0xEF000000

#define BOOT_ROM_LENGTH		0x8000



/* Level 1 Memory */

include/asm-blackfin/mach-bf533/mem_map.h

+1 −1
Original line number Diff line number Diff line 


/*

 * File:         include/asm-blackfin/mach-bf533/mem_map.h

 * Based on:
@@ -48,6 +47,7 @@ 
/* Boot ROM Memory */



#define BOOT_ROM_START		0xEF000000

#define BOOT_ROM_LENGTH		0x400



/* Level 1 Memory */

include/asm-blackfin/mach-bf537/mem_map.h

+1 −0
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ 
/* Boot ROM Memory */



#define BOOT_ROM_START		0xEF000000

#define BOOT_ROM_LENGTH		0x800



/* Level 1 Memory */

include/asm-blackfin/mach-bf548/mem_map.h

+11 −0
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ 
/* Boot ROM Memory */



#define BOOT_ROM_START		0xEF000000

#define BOOT_ROM_LENGTH		0x1000



/* Level 1 Memory */
@@ -87,6 +88,16 @@ 
#define BFIN_DSUPBANKS	0

#endif /*CONFIG_BFIN_DCACHE*/



/* Level 2 Memory */

#if !defined(CONFIG_BF542)

# define L2_START          0xFEB00000

# if defined(CONFIG_BF544)

#  define L2_LENGTH        0x10000

# else

#  define L2_LENGTH        0x20000

# endif

#endif



/* Scratch Pad Memory */



#define L1_SCRATCH_START	0xFFB00000