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Commit 6ff4fd05 authored by ling.ma@intel.com's avatar ling.ma@intel.com Committed by Eric Anholt
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drm/i915: Set SSC frequency for 8xx chips correctly 



All 8xx class chips have the 66/48 split, not just 855.

Signed-off-by: default avatarMa Ling <ling.ma@intel.com>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent 7662c8bd
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