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Commit 44264261 authored by Venkatesh Pallipadi's avatar Venkatesh Pallipadi Committed by Andi Kleen
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[PATCH] i386: Handle 32 bit PerfMon Counter writes cleanly in oprofile 



Handle these 32 bit perfmon counter MSR writes cleanly in oprofile.

Signed-off-by: default avatarVenkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: default avatarAndi Kleen <ak@suse.de>
parent 90ce4bc4

arch/i386/oprofile/op_model_ppro.c

+5 −4
Original line number Diff line number Diff line
@@ -24,7 +24,8 @@ 


#define CTR_IS_RESERVED(msrs,c) (msrs->counters[(c)].addr ? 1 : 0)

#define CTR_READ(l,h,msrs,c) do {rdmsr(msrs->counters[(c)].addr, (l), (h));} while (0)

#define CTR_WRITE(l,msrs,c) do {wrmsr(msrs->counters[(c)].addr, -(u32)(l), -1);} while (0)

#define CTR_32BIT_WRITE(l,msrs,c)	\

	do {wrmsr(msrs->counters[(c)].addr, -(u32)(l), 0);} while (0)

#define CTR_OVERFLOWED(n) (!((n) & (1U<<31)))



#define CTRL_IS_RESERVED(msrs,c) (msrs->controls[(c)].addr ? 1 : 0)
@@ -79,7 +80,7 @@ static void ppro_setup_ctrs(struct op_msrs const * const msrs) 
	for (i = 0; i < NUM_COUNTERS; ++i) {

		if (unlikely(!CTR_IS_RESERVED(msrs,i)))

			continue;

		CTR_WRITE(1, msrs, i);

		CTR_32BIT_WRITE(1, msrs, i);

	}



	/* enable active counters */
@@ -87,7 +88,7 @@ static void ppro_setup_ctrs(struct op_msrs const * const msrs) 
		if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs,i))) {

			reset_value[i] = counter_config[i].count;



			CTR_WRITE(counter_config[i].count, msrs, i);

			CTR_32BIT_WRITE(counter_config[i].count, msrs, i);



			CTRL_READ(low, high, msrs, i);

			CTRL_CLEAR(low);
@@ -116,7 +117,7 @@ static int ppro_check_ctrs(struct pt_regs * const regs, 
		CTR_READ(low, high, msrs, i);

		if (CTR_OVERFLOWED(low)) {

			oprofile_add_sample(regs, i);

			CTR_WRITE(reset_value[i], msrs, i);

			CTR_32BIT_WRITE(reset_value[i], msrs, i);

		}

	}