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Commit 3f35d1f5 authored by Uwe Kleine-König's avatar Uwe Kleine-König
Browse files

imx/mach-mx2: use constants namespaced by the corresponding SOC (easy part) 



This just leaves devices.c, generic.c and serial.c to clean up.  As
these files are used on more than one SOC they need some more work.

Signed-off-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Holger Schurig <hs4233@mail.mn-solutions.de>
Cc: Rabin Vincent <rabin@rab.in>
Cc: Javier Martin <javier.martin@vista-silicon.com>
Cc: Valentin Longchamp <valentin.longchamp@epfl.ch>
Cc: Jean Delvare <khali@linux-fr.org>
Cc: Eric Benard <eric@eukrea.com>
Cc: Ivo Clarysse <ivo.clarysse@gmail.com>
Cc: Vladimir Barinov <vbarinov@embeddedalley.com>
Cc: Daniel Schaeffer <daniel.schaeffer@timesys.com>
Cc: Simon POLETTE <spolette@adnlysd018.(none)>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Alan Carvalho de Assis <acassis@gmail.com>
Cc: Luotao Fu <l.fu@pengutronix.de>
parent b7056468

arch/arm/mach-mx2/clock_imx21.c

+3 −2
Original line number Diff line number Diff line
@@ -28,7 +28,7 @@ 
#include <asm/clkdev.h>

#include <asm/div64.h>



#define IO_ADDR_CCM(off)	(IO_ADDRESS(CCM_BASE_ADDR) + (off))

#define IO_ADDR_CCM(off)	(IO_ADDRESS(MX21_CCM_BASE_ADDR) + (off))



/* Register offsets */

#define CCM_CSCR		IO_ADDR_CCM(0x0)
@@ -1235,6 +1235,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href) 
	clk_enable(&uart_clk[0]);

#endif



	mxc_timer_init(&gpt_clk[0], IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1);

	mxc_timer_init(&gpt_clk[0], IO_ADDRESS(MX21_GPT1_BASE_ADDR),

			MX21_INT_GPT1);

	return 0;

}

arch/arm/mach-mx2/clock_imx27.c

+3 −2
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ 
#include <mach/common.h>

#include <mach/hardware.h>



#define IO_ADDR_CCM(off)	(IO_ADDRESS(CCM_BASE_ADDR) + (off))

#define IO_ADDR_CCM(off)	(IO_ADDRESS(MX27_CCM_BASE_ADDR) + (off))



/* Register offsets */

#define CCM_CSCR		IO_ADDR_CCM(0x0)
@@ -757,7 +757,8 @@ int __init mx27_clocks_init(unsigned long fref) 
	clk_enable(&uart1_clk);

#endif



	mxc_timer_init(&gpt1_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1);

	mxc_timer_init(&gpt1_clk, IO_ADDRESS(MX27_GPT1_BASE_ADDR),

			MX27_INT_GPT1);



	return 0;

}

arch/arm/mach-mx2/cpu_imx27.c

+1 −1
Original line number Diff line number Diff line
@@ -39,7 +39,7 @@ static void query_silicon_parameter(void) 
	 * the silicon revision very early we read it here to

	 * avoid any further hooks

	*/

	val = __raw_readl(IO_ADDRESS(SYSCTRL_BASE_ADDR) + SYS_CHIP_ID);

	val = __raw_readl(IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR) + SYS_CHIP_ID);



	cpu_silicon_rev = (int)(val >> 28);

	cpu_partnumber = (int)((val >> 12) & 0xFFFF);

arch/arm/mach-mx2/eukrea_cpuimx27.c

+6 −6
Original line number Diff line number Diff line
@@ -142,28 +142,28 @@ static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = { 
#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)

static struct plat_serial8250_port serial_platform_data[] = {

	{

		.mapbase = (unsigned long)(CS3_BASE_ADDR + 0x200000),

		.mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x200000),

		.irq = IRQ_GPIOB(23),

		.uartclk = 14745600,

		.regshift = 1,

		.iotype = UPIO_MEM,

		.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,

	}, {

		.mapbase = (unsigned long)(CS3_BASE_ADDR + 0x400000),

		.mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x400000),

		.irq = IRQ_GPIOB(22),

		.uartclk = 14745600,

		.regshift = 1,

		.iotype = UPIO_MEM,

		.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,

	}, {

		.mapbase = (unsigned long)(CS3_BASE_ADDR + 0x800000),

		.mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x800000),

		.irq = IRQ_GPIOB(27),

		.uartclk = 14745600,

		.regshift = 1,

		.iotype = UPIO_MEM,

		.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,

	}, {

		.mapbase = (unsigned long)(CS3_BASE_ADDR + 0x1000000),

		.mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x1000000),

		.irq = IRQ_GPIOB(30),

		.uartclk = 14745600,

		.regshift = 1,
@@ -224,8 +224,8 @@ static struct sys_timer eukrea_cpuimx27_timer = { 
};



MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")

	.phys_io        = AIPI_BASE_ADDR,

	.io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,

	.phys_io        = MX27_AIPI_BASE_ADDR,

	.io_pg_offst    = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,

	.boot_params    = PHYS_OFFSET + 0x100,

	.map_io         = mx27_map_io,

	.init_irq       = mx27_init_irq,

arch/arm/mach-mx2/mx21ads.c

+5 −5
Original line number Diff line number Diff line
@@ -118,8 +118,8 @@ static struct physmap_flash_data mx21ads_flash_data = { 
};



static struct resource mx21ads_flash_resource = {

	.start = CS0_BASE_ADDR,

	.end = CS0_BASE_ADDR + 0x02000000 - 1,

	.start = MX21_CS0_BASE_ADDR,

	.end = MX21_CS0_BASE_ADDR + 0x02000000 - 1,

	.flags = IORESOURCE_MEM,

};
@@ -242,7 +242,7 @@ static struct map_desc mx21ads_io_desc[] __initdata = { 
	 */

	{

		.virtual = MX21ADS_MMIO_BASE_ADDR,

		.pfn = __phys_to_pfn(CS1_BASE_ADDR),

		.pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR),

		.length = MX21ADS_MMIO_SIZE,

		.type = MT_DEVICE,

	},
@@ -284,8 +284,8 @@ static struct sys_timer mx21ads_timer = { 


MACHINE_START(MX21ADS, "Freescale i.MX21ADS")

	/* maintainer: Freescale Semiconductor, Inc. */

	.phys_io        = AIPI_BASE_ADDR,

	.io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,

	.phys_io        = MX21_AIPI_BASE_ADDR,

	.io_pg_offst    = ((MX21_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,

	.boot_params    = PHYS_OFFSET + 0x100,

	.map_io         = mx21ads_map_io,

	.init_irq       = mx21_init_irq,