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Commit 4e6ce4dc authored by Miaoqing Pan's avatar Miaoqing Pan Committed by John W. Linville
Browse files

ath9k: Fix RTC_DERIVED_CLK usage 



Based on the reference clock, which could be 25MHz or 40MHz,
AR_RTC_DERIVED_CLK is programmed differently for AR9340 and AR9550.
But, when a chip reset is done, processing the initvals
sets the register back to the default value.

Fix this by moving the code in ath9k_hw_init_pll() to
ar9003_hw_override_ini(). Also, do this override for AR9531.

Cc: stable@vger.kernel.org
Signed-off-by: default avatarMiaoqing Pan <miaoqing@qca.qualcomm.com>
Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 0cd75b19

drivers/net/wireless/ath/ath9k/ar9003_phy.c

+13 −0
Original line number Diff line number Diff line
@@ -664,6 +664,19 @@ static void ar9003_hw_override_ini(struct ath_hw *ah) 
		ah->enabled_cals |= TX_CL_CAL;

	else

		ah->enabled_cals &= ~TX_CL_CAL;



	if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah)) {

		if (ah->is_clk_25mhz) {

			REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);

			REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);

			REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);

		} else {

			REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);

			REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);

			REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);

		}

		udelay(100);

	}

}



static void ar9003_hw_prog_ini(struct ath_hw *ah,

drivers/net/wireless/ath/ath9k/hw.c

+0 −13
Original line number Diff line number Diff line
@@ -861,19 +861,6 @@ static void ath9k_hw_init_pll(struct ath_hw *ah, 
	udelay(RTC_PLL_SETTLE_DELAY);



	REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);



	if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {

		if (ah->is_clk_25mhz) {

			REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);

			REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);

			REG_WRITE(ah,  AR_SLP32_INC, 0x0001e7ae);

		} else {

			REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);

			REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);

			REG_WRITE(ah,  AR_SLP32_INC, 0x0001e800);

		}

		udelay(100);

	}

}



static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,