Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ffe0b2ff authored by Bjorn Helgaas's avatar Bjorn Helgaas Committed by Jeff Kirsher
Browse files

e1000e: Use standard #defines for PCIe Capability ASPM fields



Use the standard #defines for PCIe Capability ASPM fields.

Previously we used PCIE_LINK_STATE_L0S and PCIE_LINK_STATE_L1 directly, but
these are defined for the Linux ASPM interfaces, e.g.,
pci_disable_link_state(), and only coincidentally match the actual register
bits.  PCIE_LINK_STATE_CLKPM, also part of that interface, does not match
the register bit.

Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
CC: e1000-devel@lists.sourceforge.net
Acked-by: default avatarBruce Allan <bruce.w.allan@intel.com>
Tested-by: default avatarAaron Brown <aaron.f.brown@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 203e4151
Loading
Loading
Loading
Loading
+9 −2
Original line number Diff line number Diff line
@@ -5548,14 +5548,21 @@ static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
#else
static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
{
	u16 aspm_ctl = 0;

	if (state & PCIE_LINK_STATE_L0S)
		aspm_ctl |= PCI_EXP_LNKCTL_ASPM_L0S;
	if (state & PCIE_LINK_STATE_L1)
		aspm_ctl |= PCI_EXP_LNKCTL_ASPM_L1;

	/* Both device and parent should have the same ASPM setting.
	 * Disable ASPM in downstream component first and then upstream.
	 */
	pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, state);
	pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_ctl);

	if (pdev->bus->self)
		pcie_capability_clear_word(pdev->bus->self, PCI_EXP_LNKCTL,
					   state);
					   aspm_ctl);
}
#endif
static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)