clk: qcom: gcc-sm8150: Update the halt_check flag for the PCIe pipe clocks (fc57c043) · Commits · e / devices / android_kernel_xiaomi_sm6125

The gcc_pcie_0_pipe_clk and gcc_pcie_1_pipe_clk clocks are sourced off of the PCIe PHY. There's a circular dependency between the PHY and its corresponding pipe clock where the pipe clock does not turn on until the PHY is up but the PHY itself relies on a feedback signal from the pipe clock for it to turn on. This results in a long delay whilst enabling the pipe clocks, greater than 1 msec in some instances. Since it's not advisable for the clock driver to hold on to a spinlock whilst disabling interrupts for so long, move the status check to the PCIe client driver instead. Change-Id: I9da4bcf9b20dc1c5c763cd6331b55ae5437c9efb Signed-off-by:

Deepak Katragadda <dkatraga@codeaurora.org>

drivers/clk/qcom/gcc-sm8150.c

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -2276,7 +2276,7 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {

	static struct clk_branch gcc_pcie_0_pipe_clk = {		static struct clk_branch gcc_pcie_0_pipe_clk = {
	.halt_reg = 0x6b024,		.halt_reg = 0x6b024,
	.halt_check = BRANCH_VOTED,		.halt_check = BRANCH_HALT_DELAY,
	.clkr = {		.clkr = {
	.enable_reg = 0x5200c,		.enable_reg = 0x5200c,
	.enable_mask = BIT(4),		.enable_mask = BIT(4),
	@@ -2376,7 +2376,7 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = {

	static struct clk_branch gcc_pcie_1_pipe_clk = {		static struct clk_branch gcc_pcie_1_pipe_clk = {
	.halt_reg = 0x8d024,		.halt_reg = 0x8d024,
	.halt_check = BRANCH_VOTED,		.halt_check = BRANCH_HALT_DELAY,
	.clkr = {		.clkr = {
	.enable_reg = 0x52004,		.enable_reg = 0x52004,
	.enable_mask = BIT(30),		.enable_mask = BIT(30),