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Commit fbf8d2be authored by Odelu Kukatla's avatar Odelu Kukatla Committed by Gerrit - the friendly Code Review server
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clk: qcom: smd: Add support for rpm clocks for TRINKET 



Add rpm smd clocks, PMIC and bus clocks which are required on
TRINKET for clients to vote on. Keep active only vote on XO
and 19.2MHz vote on cnoc and snoc clocks.

Change-Id: Ife815cd4f4a0a49cd0f60350fc42e7dfe86ff41b
Signed-off-by: default avatarOdelu Kukatla <okukatla@codeaurora.org>
parent 9f512d30

Documentation/devicetree/bindings/clock/qcom,rpmcc.txt

+1 −0
Original line number Original line Diff line number Diff line
@@ -14,6 +14,7 @@ Required properties : 
			"qcom,rpmcc-msm8974", "qcom,rpmcc"

			"qcom,rpmcc-msm8974", "qcom,rpmcc"

			"qcom,rpmcc-apq8064", "qcom,rpmcc"

			"qcom,rpmcc-apq8064", "qcom,rpmcc"

			"qcom,rpmcc-qcs405", "qcom,rpmcc"

			"qcom,rpmcc-qcs405", "qcom,rpmcc"

			"qcom,rpmcc-trinket", "qcom,rpmcc"





- #clock-cells : shall contain 1

- #clock-cells : shall contain 1

drivers/clk/qcom/clk-smd-rpm.c

+125 −2
Original line number Original line Diff line number Diff line 
/*

/*

 * Copyright (c) 2016, Linaro Limited

 * Copyright (c) 2016, Linaro Limited

 * Copyright (c) 2014, 2016-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2014, 2016-2019, The Linux Foundation. All rights reserved.

 *

 *

 * This software is licensed under the terms of the GNU General Public

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and

 * License version 2, as published by the Free Software Foundation, and
@@ -709,10 +709,112 @@ static const struct rpm_smd_clk_desc rpm_clk_qcs405 = { 
	.num_clks = ARRAY_SIZE(qcs405_clks),

	.num_clks = ARRAY_SIZE(qcs405_clks),

};

};





/* Trinket */

DEFINE_CLK_SMD_RPM_BRANCH(trinket, bi_tcxo, bi_tcxo_ao,

					QCOM_SMD_RPM_MISC_CLK, 0, 19200000);

DEFINE_CLK_SMD_RPM(trinket, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);

DEFINE_CLK_SMD_RPM(trinket, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);

DEFINE_CLK_SMD_RPM(trinket, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);

DEFINE_CLK_SMD_RPM_QDSS(trinket, qdss_clk, qdss_a_clk,

						QCOM_SMD_RPM_MISC_CLK, 1);

DEFINE_CLK_SMD_RPM(trinket, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);

DEFINE_CLK_SMD_RPM(trinket, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);

DEFINE_CLK_SMD_RPM(trinket, qup_clk, qup_a_clk, QCOM_SMD_RPM_QUP_CLK, 0);

DEFINE_CLK_SMD_RPM(trinket, mmnrt_clk, mmnrt_a_clk, QCOM_SMD_RPM_MMXI_CLK, 0);

DEFINE_CLK_SMD_RPM(trinket, mmrt_clk, mmrt_a_clk, QCOM_SMD_RPM_MMXI_CLK, 1);

DEFINE_CLK_SMD_RPM(trinket, snoc_periph_clk, snoc_periph_a_clk,

						QCOM_SMD_RPM_BUS_CLK, 0);

DEFINE_CLK_SMD_RPM(trinket, snoc_lpass_clk, snoc_lpass_a_clk,

						QCOM_SMD_RPM_BUS_CLK, 5);



/* SMD_XO_BUFFER */

DEFINE_CLK_SMD_RPM_XO_BUFFER(trinket, ln_bb_clk1, ln_bb_clk1_a, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER(trinket, ln_bb_clk2, ln_bb_clk2_a, 2);

DEFINE_CLK_SMD_RPM_XO_BUFFER(trinket, ln_bb_clk3, ln_bb_clk3_a, 3);

DEFINE_CLK_SMD_RPM_XO_BUFFER(trinket, rf_clk1, rf_clk1_a, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER(trinket, rf_clk2, rf_clk2_a, 5);



/* Voter clocks */

static DEFINE_CLK_VOTER(cnoc_msmbus_clk, cnoc_clk, LONG_MAX);

static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, cnoc_a_clk, LONG_MAX);

static DEFINE_CLK_VOTER(cnoc_keepalive_a_clk, cnoc_a_clk, LONG_MAX);

static DEFINE_CLK_VOTER(snoc_keepalive_a_clk, snoc_a_clk, LONG_MAX);



/* Branch Voter clocks */

static DEFINE_CLK_BRANCH_VOTER(bi_tcxo_otg_clk, bi_tcxo);

static DEFINE_CLK_BRANCH_VOTER(bi_tcxo_pil_pronto_clk, bi_tcxo);

static DEFINE_CLK_BRANCH_VOTER(bi_tcxo_pil_mss_clk, bi_tcxo);

static DEFINE_CLK_BRANCH_VOTER(bi_tcxo_wlan_clk, bi_tcxo);

static DEFINE_CLK_BRANCH_VOTER(bi_tcxo_pil_lpass_clk, bi_tcxo);

static DEFINE_CLK_BRANCH_VOTER(bi_tcxo_pil_cdsp_clk, bi_tcxo);



static struct clk_hw *trinket_clks[] = {

	[RPM_SMD_XO_CLK_SRC] = &trinket_bi_tcxo.hw,

	[RPM_SMD_XO_A_CLK_SRC] = &trinket_bi_tcxo_ao.hw,

	[RPM_SMD_SNOC_CLK] = &trinket_snoc_clk.hw,

	[RPM_SMD_SNOC_A_CLK] = &trinket_snoc_a_clk.hw,

	[RPM_SMD_BIMC_CLK] = &trinket_bimc_clk.hw,

	[RPM_SMD_BIMC_A_CLK] = &trinket_bimc_a_clk.hw,

	[RPM_SMD_QDSS_CLK] = &trinket_qdss_clk.hw,

	[RPM_SMD_QDSS_A_CLK] = &trinket_qdss_a_clk.hw,

	[RPM_SMD_RF_CLK1] = &trinket_rf_clk1.hw,

	[RPM_SMD_RF_CLK1_A] = &trinket_rf_clk1_a.hw,

	[RPM_SMD_RF_CLK2] = &trinket_rf_clk2.hw,

	[RPM_SMD_RF_CLK2_A] = &trinket_rf_clk2_a.hw,

	[RPM_SMD_LN_BB_CLK1] = &trinket_ln_bb_clk1.hw,

	[RPM_SMD_LN_BB_CLK1_A] = &trinket_ln_bb_clk1_a.hw,

	[RPM_SMD_LN_BB_CLK2] = &trinket_ln_bb_clk2.hw,

	[RPM_SMD_LN_BB_CLK2_A] = &trinket_ln_bb_clk2_a.hw,

	[RPM_SMD_LN_BB_CLK3] = &trinket_ln_bb_clk3.hw,

	[RPM_SMD_LN_BB_CLK3_A] = &trinket_ln_bb_clk3_a.hw,

	[RPM_SMD_CNOC_CLK] = &trinket_cnoc_clk.hw,

	[RPM_SMD_CNOC_A_CLK] = &trinket_cnoc_a_clk.hw,

	[RPM_SMD_CE1_CLK] = &trinket_ce1_clk.hw,

	[RPM_SMD_CE1_A_CLK] = &trinket_ce1_a_clk.hw,

	[CNOC_MSMBUS_CLK] = &cnoc_msmbus_clk.hw,

	[CNOC_MSMBUS_A_CLK] = &cnoc_msmbus_a_clk.hw,

	[SNOC_KEEPALIVE_A_CLK] = &snoc_keepalive_a_clk.hw,

	[CNOC_KEEPALIVE_A_CLK] = &cnoc_keepalive_a_clk.hw,

	[SNOC_MSMBUS_CLK] = &snoc_msmbus_clk.hw,

	[SNOC_MSMBUS_A_CLK] = &snoc_msmbus_a_clk.hw,

	[BIMC_MSMBUS_CLK] = &bimc_msmbus_clk.hw,

	[BIMC_MSMBUS_A_CLK] = &bimc_msmbus_a_clk.hw,

	[MCD_CE1_CLK] = &mcd_ce1_clk.hw,

	[QCEDEV_CE1_CLK] = &qcedev_ce1_clk.hw,

	[QCRYPTO_CE1_CLK] = &qcrypto_ce1_clk.hw,

	[QSEECOM_CE1_CLK] = &qseecom_ce1_clk.hw,

	[SCM_CE1_CLK] = &scm_ce1_clk.hw,

	[CXO_SMD_OTG_CLK] = &bi_tcxo_otg_clk.hw,

	[CXO_SMD_PIL_PRONTO_CLK] = &bi_tcxo_pil_pronto_clk.hw,

	[CXO_SMD_PIL_MSS_CLK] = &bi_tcxo_pil_mss_clk.hw,

	[CXO_SMD_WLAN_CLK] = &bi_tcxo_wlan_clk.hw,

	[CXO_SMD_PIL_LPASS_CLK] = &bi_tcxo_pil_lpass_clk.hw,

	[CXO_SMD_PIL_CDSP_CLK] = &bi_tcxo_pil_cdsp_clk.hw,

	[RPM_SMD_IPA_CLK] = &trinket_ipa_clk.hw,

	[RPM_SMD_IPA_A_CLK] = &trinket_ipa_a_clk.hw,

	[RPM_SMD_QUP_CLK] = &trinket_qup_clk.hw,

	[RPM_SMD_QUP_A_CLK] = &trinket_qup_a_clk.hw,

	[RPM_SMD_MMRT_CLK] = &trinket_mmrt_clk.hw,

	[RPM_SMD_MMRT_A_CLK] = &trinket_mmrt_a_clk.hw,

	[RPM_SMD_MMNRT_CLK] = &trinket_mmnrt_clk.hw,

	[RPM_SMD_MMNRT_A_CLK] = &trinket_mmnrt_a_clk.hw,

	[RPM_SMD_SNOC_PERIPH_CLK] = &trinket_snoc_periph_clk.hw,

	[RPM_SMD_SNOC_PERIPH_A_CLK] = &trinket_snoc_periph_a_clk.hw,

	[RPM_SMD_SNOC_LPASS_CLK] = &trinket_snoc_lpass_clk.hw,

	[RPM_SMD_SNOC_LPASS_A_CLK] = &trinket_snoc_lpass_a_clk.hw,

};



static const struct rpm_smd_clk_desc rpm_clk_trinket = {

	.clks = trinket_clks,

	.num_rpm_clks = RPM_SMD_LN_BB_CLK3_A,

	.num_clks = ARRAY_SIZE(trinket_clks),

};



static const struct of_device_id rpm_smd_clk_match_table[] = {

static const struct of_device_id rpm_smd_clk_match_table[] = {

	{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },

	{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },

	{ .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },

	{ .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },

	{ .compatible = "qcom,rpmcc-qcs405",  .data = &rpm_clk_qcs405  },

	{ .compatible = "qcom,rpmcc-qcs405",  .data = &rpm_clk_qcs405  },

	{ .compatible = "qcom,rpmcc-trinket", .data = &rpm_clk_trinket  },

	{ }

	{ }

};

};

MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);

MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
@@ -723,17 +825,24 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) 
	struct clk *clk;

	struct clk *clk;

	struct rpm_cc *rcc;

	struct rpm_cc *rcc;

	struct clk_onecell_data *data;

	struct clk_onecell_data *data;

	int ret, is_qcs405;

	int ret, is_qcs405, is_trinket;

	size_t num_clks, i;

	size_t num_clks, i;

	struct clk_hw **hw_clks;

	struct clk_hw **hw_clks;

	const struct rpm_smd_clk_desc *desc;

	const struct rpm_smd_clk_desc *desc;





	is_qcs405 = of_device_is_compatible(pdev->dev.of_node,

	is_qcs405 = of_device_is_compatible(pdev->dev.of_node,

						"qcom,rpmcc-qcs405");

						"qcom,rpmcc-qcs405");



	is_trinket = of_device_is_compatible(pdev->dev.of_node,

						"qcom,rpmcc-trinket");

	if (is_qcs405) {

	if (is_qcs405) {

		ret = clk_vote_bimc(&qcs405_bimc_clk.hw, INT_MAX);

		ret = clk_vote_bimc(&qcs405_bimc_clk.hw, INT_MAX);

		if (ret < 0)

		if (ret < 0)

			return ret;

			return ret;

	} else if (is_trinket) {

		ret = clk_vote_bimc(&trinket_bimc_clk.hw, INT_MAX);

		if (ret < 0)

			return ret;

	}

	}





	desc = of_device_get_match_data(&pdev->dev);

	desc = of_device_get_match_data(&pdev->dev);
@@ -809,6 +918,20 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) 
		/* Hold an active set vote for the pnoc_keepalive_a_clk */

		/* Hold an active set vote for the pnoc_keepalive_a_clk */

		clk_set_rate(pnoc_keepalive_a_clk.hw.clk, 19200000);

		clk_set_rate(pnoc_keepalive_a_clk.hw.clk, 19200000);

		clk_prepare_enable(pnoc_keepalive_a_clk.hw.clk);

		clk_prepare_enable(pnoc_keepalive_a_clk.hw.clk);

	} else if (is_trinket) {

		/*

		 * Keep an active vote on CXO in case no other driver

		 * votes for it.

		 */

		clk_prepare_enable(trinket_bi_tcxo_ao.hw.clk);



		/* Hold an active set vote for the cnoc_keepalive_a_clk */

		clk_set_rate(cnoc_keepalive_a_clk.hw.clk, 19200000);

		clk_prepare_enable(cnoc_keepalive_a_clk.hw.clk);



		/* Hold an active set vote for the snoc_keepalive_a_clk */

		clk_set_rate(snoc_keepalive_a_clk.hw.clk, 19200000);

		clk_prepare_enable(snoc_keepalive_a_clk.hw.clk);

	}

	}





	dev_info(&pdev->dev, "Registered RPM clocks\n");

	dev_info(&pdev->dev, "Registered RPM clocks\n");

include/dt-bindings/clock/qcom,rpmcc.h

+115 −93
Original line number Original line Diff line number Diff line
@@ -49,98 +49,120 @@ 
#define RPM_SMD_BIMC_A_CLK				7

#define RPM_SMD_BIMC_A_CLK				7

#define RPM_SMD_QDSS_CLK				8

#define RPM_SMD_QDSS_CLK				8

#define RPM_SMD_QDSS_A_CLK				9

#define RPM_SMD_QDSS_A_CLK				9

#define RPM_SMD_BB_CLK1				10

#define RPM_SMD_IPA_CLK				10

#define RPM_SMD_BB_CLK1_A				11

#define RPM_SMD_IPA_A_CLK				11

#define RPM_SMD_BB_CLK2				12

#define RPM_SMD_QUP_CLK				12

#define RPM_SMD_BB_CLK2_A				13

#define RPM_SMD_QUP_A_CLK				13

#define RPM_SMD_RF_CLK1				14

#define RPM_SMD_MMRT_CLK				14

#define RPM_SMD_RF_CLK1_A				15

#define RPM_SMD_MMRT_A_CLK				15

#define RPM_SMD_RF_CLK2				16

#define RPM_SMD_MMNRT_CLK				16

#define RPM_SMD_RF_CLK2_A				17

#define RPM_SMD_MMNRT_A_CLK				17

#define RPM_SMD_BB_CLK1_PIN				18

#define RPM_SMD_SNOC_PERIPH_CLK				18

#define RPM_SMD_BB_CLK1_A_PIN			19

#define RPM_SMD_SNOC_PERIPH_A_CLK				19

#define RPM_SMD_BB_CLK2_PIN				20

#define RPM_SMD_SNOC_LPASS_CLK				20

#define RPM_SMD_BB_CLK2_A_PIN			21

#define RPM_SMD_SNOC_LPASS_A_CLK				21

#define RPM_SMD_RF_CLK1_PIN				22

#define RPM_SMD_BB_CLK1				22

#define RPM_SMD_RF_CLK1_A_PIN			23

#define RPM_SMD_BB_CLK1_A				23

#define RPM_SMD_RF_CLK2_PIN				24

#define RPM_SMD_BB_CLK2					24

#define RPM_SMD_RF_CLK2_A_PIN			25

#define RPM_SMD_BB_CLK2_A				25

#define RPM_SMD_PNOC_CLK			26

#define RPM_SMD_RF_CLK1				26

#define RPM_SMD_PNOC_A_CLK			27

#define RPM_SMD_RF_CLK1_A				27

#define RPM_SMD_CNOC_CLK			28

#define RPM_SMD_RF_CLK2				28

#define RPM_SMD_CNOC_A_CLK			29

#define RPM_SMD_RF_CLK2_A				29

#define RPM_SMD_MMSSNOC_AHB_CLK			30

#define RPM_SMD_BB_CLK1_PIN				30

#define RPM_SMD_MMSSNOC_AHB_A_CLK		31

#define RPM_SMD_BB_CLK1_A_PIN			31

#define RPM_SMD_GFX3D_CLK_SRC			32

#define RPM_SMD_BB_CLK2_PIN				32

#define RPM_SMD_GFX3D_A_CLK_SRC			33

#define RPM_SMD_BB_CLK2_A_PIN			33

#define RPM_SMD_OCMEMGX_CLK			34

#define RPM_SMD_RF_CLK1_PIN				34

#define RPM_SMD_OCMEMGX_A_CLK			35

#define RPM_SMD_RF_CLK1_A_PIN			35

#define RPM_SMD_CXO_D0				36

#define RPM_SMD_RF_CLK2_PIN				36

#define RPM_SMD_CXO_D0_A			37

#define RPM_SMD_RF_CLK2_A_PIN			37

#define RPM_SMD_CXO_D1				38

#define RPM_SMD_PNOC_CLK			38

#define RPM_SMD_CXO_D1_A			39

#define RPM_SMD_PNOC_A_CLK			39

#define RPM_SMD_CXO_A0				40

#define RPM_SMD_CNOC_CLK			40

#define RPM_SMD_CXO_A0_A			41

#define RPM_SMD_CNOC_A_CLK			41

#define RPM_SMD_CXO_A1				42

#define RPM_SMD_MMSSNOC_AHB_CLK			42

#define RPM_SMD_CXO_A1_A			43

#define RPM_SMD_MMSSNOC_AHB_A_CLK		43

#define RPM_SMD_CXO_A2				44

#define RPM_SMD_GFX3D_CLK_SRC			44

#define RPM_SMD_CXO_A2_A			45

#define RPM_SMD_GFX3D_A_CLK_SRC			45

#define RPM_SMD_DIV_CLK1			46

#define RPM_SMD_OCMEMGX_CLK			46

#define RPM_SMD_DIV_A_CLK1			47

#define RPM_SMD_OCMEMGX_A_CLK			47

#define RPM_SMD_DIV_CLK2			48

#define RPM_SMD_CXO_D0				48

#define RPM_SMD_DIV_A_CLK2			49

#define RPM_SMD_CXO_D0_A			49

#define RPM_SMD_DIFF_CLK			50

#define RPM_SMD_CXO_D1				50

#define RPM_SMD_DIFF_A_CLK			51

#define RPM_SMD_CXO_D1_A			51

#define RPM_SMD_CXO_D0_PIN			52

#define RPM_SMD_CXO_A0				52

#define RPM_SMD_CXO_D0_A_PIN			53

#define RPM_SMD_CXO_A0_A			53

#define RPM_SMD_CXO_D1_PIN			54

#define RPM_SMD_CXO_A1				54

#define RPM_SMD_CXO_D1_A_PIN			55

#define RPM_SMD_CXO_A1_A			55

#define RPM_SMD_CXO_A0_PIN			56

#define RPM_SMD_CXO_A2				56

#define RPM_SMD_CXO_A0_A_PIN			57

#define RPM_SMD_CXO_A2_A			57

#define RPM_SMD_CXO_A1_PIN			58

#define RPM_SMD_DIV_CLK1			58

#define RPM_SMD_CXO_A1_A_PIN			59

#define RPM_SMD_DIV_A_CLK1			59

#define RPM_SMD_CXO_A2_PIN			60

#define RPM_SMD_DIV_CLK2			60

#define RPM_SMD_CXO_A2_A_PIN			61

#define RPM_SMD_DIV_A_CLK2			61

#define RPM_SMD_QPIC_CLK			64

#define RPM_SMD_DIFF_CLK			62

#define RPM_SMD_QPIC_A_CLK			65

#define RPM_SMD_DIFF_A_CLK			63

#define RPM_SMD_CE1_CLK				66

#define RPM_SMD_CXO_D0_PIN			64

#define RPM_SMD_CE1_A_CLK			67

#define RPM_SMD_CXO_D0_A_PIN			65

#define RPM_SMD_BIMC_GPU_CLK                    68

#define RPM_SMD_CXO_D1_PIN			66

#define RPM_SMD_BIMC_GPU_A_CLK                  69

#define RPM_SMD_CXO_D1_A_PIN			67

#define RPM_SMD_LN_BB_CLK			70

#define RPM_SMD_CXO_A0_PIN			68

#define RPM_SMD_LN_BB_CLK_A			71

#define RPM_SMD_CXO_A0_A_PIN			69

#define RPM_SMD_LN_BB_CLK_PIN			72

#define RPM_SMD_CXO_A1_PIN			70

#define RPM_SMD_LN_BB_CLK_A_PIN			73

#define RPM_SMD_CXO_A1_A_PIN			71

#define RPM_SMD_RF_CLK3				74

#define RPM_SMD_CXO_A2_PIN			72

#define RPM_SMD_RF_CLK3_A			75

#define RPM_SMD_CXO_A2_A_PIN			73

#define RPM_SMD_RF_CLK3_PIN			76

#define RPM_SMD_QPIC_CLK			74

#define RPM_SMD_RF_CLK3_A_PIN			77

#define RPM_SMD_QPIC_A_CLK			75

#define PNOC_MSMBUS_CLK				78

#define RPM_SMD_CE1_CLK				76

#define PNOC_MSMBUS_A_CLK			79

#define RPM_SMD_CE1_A_CLK			77

#define PNOC_KEEPALIVE_A_CLK			80

#define RPM_SMD_BIMC_GPU_CLK				78

#define SNOC_MSMBUS_CLK				81

#define RPM_SMD_BIMC_GPU_A_CLK				79

#define SNOC_MSMBUS_A_CLK			82

#define RPM_SMD_LN_BB_CLK			80

#define BIMC_MSMBUS_CLK				83

#define RPM_SMD_LN_BB_CLK_A			81

#define BIMC_MSMBUS_A_CLK			84

#define RPM_SMD_LN_BB_CLK_PIN			82

#define PNOC_USB_CLK				85

#define RPM_SMD_LN_BB_CLK_A_PIN			83

#define PNOC_USB_A_CLK				86

#define RPM_SMD_RF_CLK3				84

#define SNOC_USB_CLK				87

#define RPM_SMD_RF_CLK3_A			85

#define SNOC_USB_A_CLK				88

#define RPM_SMD_RF_CLK3_PIN			86

#define BIMC_USB_CLK				89

#define RPM_SMD_RF_CLK3_A_PIN			87

#define BIMC_USB_A_CLK				90

#define RPM_SMD_LN_BB_CLK1				88

#define SNOC_WCNSS_A_CLK			91

#define RPM_SMD_LN_BB_CLK1_A				89

#define BIMC_WCNSS_A_CLK			92

#define RPM_SMD_LN_BB_CLK2				90

#define MCD_CE1_CLK				93

#define RPM_SMD_LN_BB_CLK2_A				91

#define QCEDEV_CE1_CLK				94

#define RPM_SMD_LN_BB_CLK3				92

#define QCRYPTO_CE1_CLK				95

#define RPM_SMD_LN_BB_CLK3_A				93

#define QSEECOM_CE1_CLK				96

#define PNOC_MSMBUS_CLK				94

#define SCM_CE1_CLK				97

#define PNOC_MSMBUS_A_CLK			95

#define CXO_SMD_OTG_CLK				98

#define PNOC_KEEPALIVE_A_CLK			96

#define CXO_SMD_LPM_CLK				99

#define SNOC_MSMBUS_CLK				97

#define CXO_SMD_PIL_PRONTO_CLK			100

#define SNOC_MSMBUS_A_CLK			98

#define CXO_SMD_PIL_MSS_CLK			101

#define BIMC_MSMBUS_CLK				99

#define CXO_SMD_WLAN_CLK			102

#define BIMC_MSMBUS_A_CLK			100

#define CXO_SMD_PIL_LPASS_CLK			103

#define PNOC_USB_CLK				101

#define CXO_SMD_PIL_CDSP_CLK			104

#define PNOC_USB_A_CLK				102

#define SNOC_USB_CLK				103

#define SNOC_USB_A_CLK				104

#define BIMC_USB_CLK				105

#define BIMC_USB_A_CLK				106

#define SNOC_WCNSS_A_CLK			107

#define BIMC_WCNSS_A_CLK			108

#define MCD_CE1_CLK				109

#define QCEDEV_CE1_CLK				110

#define QCRYPTO_CE1_CLK				111

#define QSEECOM_CE1_CLK				112

#define SCM_CE1_CLK				113

#define CXO_SMD_OTG_CLK				114

#define CXO_SMD_LPM_CLK				115

#define CXO_SMD_PIL_PRONTO_CLK			116

#define CXO_SMD_PIL_MSS_CLK			117

#define CXO_SMD_WLAN_CLK			118

#define CXO_SMD_PIL_LPASS_CLK			119

#define CXO_SMD_PIL_CDSP_CLK			120

#define CNOC_MSMBUS_CLK				121

#define CNOC_MSMBUS_A_CLK				122

#define CNOC_KEEPALIVE_A_CLK				123

#define SNOC_KEEPALIVE_A_CLK				124





#endif
 
#endif

include/linux/soc/qcom/smd-rpm.h

+3 −0
Original line number Original line Diff line number Diff line
@@ -28,6 +28,9 @@ struct qcom_smd_rpm; 
#define QCOM_SMD_RPM_SPDM	0x63707362

#define QCOM_SMD_RPM_SPDM	0x63707362

#define QCOM_SMD_RPM_VSA	0x00617376

#define QCOM_SMD_RPM_VSA	0x00617376

#define QCOM_SMD_RPM_CE_CLK	0x00006563

#define QCOM_SMD_RPM_CE_CLK	0x00006563

#define QCOM_SMD_RPM_IPA_CLK	0x00617069

#define QCOM_SMD_RPM_QUP_CLK	0x00707571

#define QCOM_SMD_RPM_MMXI_CLK	0x69786D6D





int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,

int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,

		       int state,

		       int state,