msm: ep_pcie: Update L1 programming sequence

L1 requires updated PHY which is programmed by the
HLOS driver after one cycle of D3_COLD followed by D0 entry.
The PHY sequence from PBL does not support L1 therefore
disable L1 until the new PHY sequence gets programmed.

Change-Id: I041b3e7db86d6985400ce6d218b7a363f915d9cf
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>