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Commit f694d143 authored by Ghanim Fodi's avatar Ghanim Fodi Committed by Gerrit - the friendly Code Review server
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msm: ipa: Update header register configuration for ipa4.5 



IPA4.5 introduce changes to IPA headers register configuration.
Length, size and offset fields now are wider and utilizes more
bits across the different register. This change adapt the
configuration accordingly.

CRs-Fixed: 2303588
Change-Id: Ib0d2c30519d8bc12bc1bf0a6ee82ad6388c7173c
Signed-off-by: default avatarGhanim Fodi <gfodi@codeaurora.org>
parent 753e04cd

drivers/platform/msm/ipa/ipa_v3/ipa_dp.c

+7 −0
Original line number Diff line number Diff line
@@ -3323,6 +3323,13 @@ int ipa3_sys_setup(struct ipa_sys_connect_params *sys_in, 
				result = -EFAULT;

				goto fail_and_disable_clocks;

			}

			if (ipa3_cfg_ep_hdr_ext(ipa_ep_idx,

						&sys_in->ipa_ep_cfg.hdr_ext)) {

				IPAERR("fail config hdr_ext prop of EP %d\n",

						ipa_ep_idx);

				result = -EFAULT;

				goto fail_and_disable_clocks;

			}

			if (ipa3_cfg_ep_cfg(ipa_ep_idx,

						&sys_in->ipa_ep_cfg.cfg)) {

				IPAERR("fail to configure cfg prop of EP %d\n",

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

+6 −3
Original line number Diff line number Diff line
@@ -4136,6 +4136,7 @@ int ipa3_cfg_ep_hdr_ext(u32 clnt_hdl, 


	/* copy over EP cfg */

	ep->cfg.hdr_ext = *ep_hdr_ext;

	ep->cfg.hdr_ext.hdr = &ep->cfg.hdr;



	IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl));
@@ -4729,9 +4730,11 @@ int ipa3_cfg_ep_metadata(u32 clnt_hdl, const struct ipa_ep_cfg_metadata *ep_md) 
	ep_md_reg_wrt.qmap_id = qmap_id;

	ipahal_write_reg_n_fields(IPA_ENDP_INIT_HDR_METADATA_n, clnt_hdl,

		&ep_md_reg_wrt);

	if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) {

		ipa3_ctx->ep[clnt_hdl].cfg.hdr.hdr_metadata_reg_valid = 1;

		ipahal_write_reg_n_fields(IPA_ENDP_INIT_HDR_n, clnt_hdl,

			&ipa3_ctx->ep[clnt_hdl].cfg.hdr);

	}



	IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl));

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c

+116 −11
Original line number Diff line number Diff line
@@ -1786,19 +1786,15 @@ static void ipareg_construct_endp_init_aggr_n_v4_5(enum ipahal_reg_name reg, 
		IPA_ENDP_INIT_AGGR_n_AGGR_GRAN_SEL_BMSK_V4_5);

}





static void ipareg_construct_endp_init_hdr_ext_n(enum ipahal_reg_name reg,

	const void *fields, u32 *val)

static void ipareg_construct_endp_init_hdr_ext_n_common(

	const struct ipa_ep_cfg_hdr_ext *ep_hdr_ext, u32 *val)

{

	struct ipa_ep_cfg_hdr_ext *ep_hdr_ext;

	u8 hdr_endianness;



	ep_hdr_ext = (struct ipa_ep_cfg_hdr_ext *)fields;

	hdr_endianness = ep_hdr_ext->hdr_little_endian ? 0 : 1;



	IPA_SETFIELD_IN_REG(*val, ep_hdr_ext->hdr_pad_to_alignment,

		IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_SHFT,

		IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_BMSK_v3_0);

		IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_BMSK);



	IPA_SETFIELD_IN_REG(*val, ep_hdr_ext->hdr_total_len_or_pad_offset,

		IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_SHFT,
@@ -1821,6 +1817,48 @@ static void ipareg_construct_endp_init_hdr_ext_n(enum ipahal_reg_name reg, 
		IPA_ENDP_INIT_HDR_EXT_n_HDR_ENDIANNESS_BMSK);

}



static void ipareg_construct_endp_init_hdr_ext_n(enum ipahal_reg_name reg,

	const void *fields, u32 *val)

{

	ipareg_construct_endp_init_hdr_ext_n_common(fields, val);

}



static void ipareg_construct_endp_init_hdr_ext_n_v4_5(enum ipahal_reg_name reg,

	const void *fields, u32 *val)

{

	const struct ipa_ep_cfg_hdr_ext *ep_hdr_ext =

		(const struct ipa_ep_cfg_hdr_ext *)fields;

	u32 msb;



	ipareg_construct_endp_init_hdr_ext_n_common(ep_hdr_ext, val);



	msb = ep_hdr_ext->hdr_total_len_or_pad_offset >>

		hweight_long(

		IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_BMSK);

	IPA_SETFIELD_IN_REG(*val, msb,

	 IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_SHFT_v4_5,

	 IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_BMSK_v4_5);



	if (!ep_hdr_ext->hdr) {

		IPAHAL_ERR("No header info, skipping it.\n");

		return;

	}



	msb = ep_hdr_ext->hdr->hdr_ofst_pkt_size >>

		hweight_long(IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_BMSK_v4_5);

	IPA_SETFIELD_IN_REG(*val, msb,

		IPA_ENDP_INIT_HDR_EXT_n_HDR_OFST_PKT_SIZE_MSB_SHFT_v4_5,

		IPA_ENDP_INIT_HDR_EXT_n_HDR_OFST_PKT_SIZE_MSB_BMSK_v4_5);



	msb = ep_hdr_ext->hdr->hdr_additional_const_len >>

		hweight_long(

		IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_BMSK_v4_5);

	IPA_SETFIELD_IN_REG(*val, msb,

		IPA_ENDP_INIT_HDR_EXT_n_HDR_ADDITIONAL_CONST_LEN_MSB_SHFT_v4_5,

		IPA_ENDP_INIT_HDR_EXT_n_HDR_ADDITIONAL_CONST_LEN_MSB_BMSK_v4_5

		);

}



static void ipareg_construct_endp_init_hdr_n(enum ipahal_reg_name reg,

	const void *fields, u32 *val)

{
@@ -1829,12 +1867,12 @@ static void ipareg_construct_endp_init_hdr_n(enum ipahal_reg_name reg, 
	ep_hdr = (struct ipa_ep_cfg_hdr *)fields;



	IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_metadata_reg_valid,

		IPA_ENDP_INIT_HDR_n_HDR_METADATA_REG_VALID_SHFT_v2,

		IPA_ENDP_INIT_HDR_n_HDR_METADATA_REG_VALID_BMSK_v2);

		IPA_ENDP_INIT_HDR_n_HDR_METADATA_REG_VALID_SHFT,

		IPA_ENDP_INIT_HDR_n_HDR_METADATA_REG_VALID_BMSK);



	IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_remove_additional,

		IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_SHFT_v2,

		IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_BMSK_v2);

		IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_SHFT,

		IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_BMSK);



	IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_a5_mux,

		IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_SHFT,
@@ -1865,6 +1903,59 @@ static void ipareg_construct_endp_init_hdr_n(enum ipahal_reg_name reg, 
		IPA_ENDP_INIT_HDR_n_HDR_LEN_BMSK);

}



static void ipareg_construct_endp_init_hdr_n_v4_5(enum ipahal_reg_name reg,

	const void *fields, u32 *val)

{

	struct ipa_ep_cfg_hdr *ep_hdr;

	u32 msb;



	ep_hdr = (struct ipa_ep_cfg_hdr *)fields;



	msb = ep_hdr->hdr_ofst_metadata >>

		hweight_long(IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_BMSK_v4_5);

	IPA_SETFIELD_IN_REG(*val, msb,

		IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_MSB_SHFT_v4_5,

		IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_MSB_BMSK_v4_5);



	msb = ep_hdr->hdr_len >>

		hweight_long(IPA_ENDP_INIT_HDR_n_HDR_LEN_BMSK_v4_5);

	IPA_SETFIELD_IN_REG(*val, msb,

		IPA_ENDP_INIT_HDR_n_HDR_LEN_MSB_SHFT_v4_5,

		IPA_ENDP_INIT_HDR_n_HDR_LEN_MSB_BMSK_v4_5);



	IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_remove_additional,

		IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_SHFT_v4_5,

		IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_BMSK_v4_5);



	IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_a5_mux,

		IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_SHFT_v4_5,

		IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_BMSK_v4_5);



	IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_ofst_pkt_size,

		IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_SHFT_v4_5,

		IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_BMSK_v4_5);



	IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_ofst_pkt_size_valid,

		IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_SHFT_v4_5,

		IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_BMSK_v4_5);



	IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_additional_const_len,

		IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_SHFT_v4_5,

		IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_BMSK_v4_5);



	IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_ofst_metadata,

		IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_SHFT_v4_5,

		IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_BMSK_v4_5);



	IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_ofst_metadata_valid,

		IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_SHFT_v4_5,

		IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_BMSK_v4_5);



	IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_len,

		IPA_ENDP_INIT_HDR_n_HDR_LEN_SHFT_v4_5,

		IPA_ENDP_INIT_HDR_n_HDR_LEN_BMSK_v4_5);

}



static void ipareg_construct_route(enum ipahal_reg_name reg,

	const void *fields, u32 *val)

{
@@ -2931,6 +3022,20 @@ static struct ipahal_reg_obj ipahal_reg_objs[IPA_HW_MAX][IPA_REG_MAX] = { 
	[IPA_HW_v4_5][IPA_SW_AREA_RAM_DIRECT_ACCESS_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x000010000, 0x4, 0, 0, 0},

	[IPA_HW_v4_5][IPA_ENDP_INIT_HDR_n] = {

		ipareg_construct_endp_init_hdr_n_v4_5, ipareg_parse_dummy,

		0x00000810, 0x70, 0, 31, 1},

	[IPA_HW_v4_5][IPA_ENDP_INIT_HDR_EXT_n] = {

		ipareg_construct_endp_init_hdr_ext_n_v4_5, ipareg_parse_dummy,

		0x00000814, 0x70, 0, 31, 1},

	[IPA_HW_v4_5][IPA_ENDP_INIT_HDR_METADATA_n] = {

		ipareg_construct_endp_init_hdr_metadata_n,

		ipareg_parse_dummy,

		0x0000081c, 0x70, 0, 13, 1},

	[IPA_HW_v4_5][IPA_ENDP_INIT_HDR_METADATA_MASK_n] = {

		ipareg_construct_endp_init_hdr_metadata_mask_n,

		ipareg_parse_dummy,

		0x00000818, 0x70, 13, 31, 1},

};



/*

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h

+33 −5
Original line number Diff line number Diff line
@@ -51,10 +51,31 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); 
#define IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_SHFT 0x14

#define IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_BMSK 0x4000000

#define IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_SHFT 0x1a

#define IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_BMSK_v2 0x8000000

#define IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_SHFT_v2 0x1b

#define IPA_ENDP_INIT_HDR_n_HDR_METADATA_REG_VALID_BMSK_v2 0x10000000

#define IPA_ENDP_INIT_HDR_n_HDR_METADATA_REG_VALID_SHFT_v2 0x1c

#define IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_BMSK 0x8000000

#define IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_SHFT 0x1b

#define IPA_ENDP_INIT_HDR_n_HDR_METADATA_REG_VALID_BMSK 0x10000000

#define IPA_ENDP_INIT_HDR_n_HDR_METADATA_REG_VALID_SHFT 0x1c



#define IPA_ENDP_INIT_HDR_n_HDR_LEN_BMSK_v4_5 0x3f

#define IPA_ENDP_INIT_HDR_n_HDR_LEN_SHFT_v4_5 0x0

#define IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_BMSK_v4_5 0x40

#define IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_SHFT_v4_5 0x6

#define IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_SHFT_v4_5 0x7

#define IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_BMSK_v4_5 0x1f80

#define IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_BMSK_v4_5 0x7e000

#define IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_SHFT_v4_5 0xd

#define IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_BMSK_v4_5 0x80000

#define IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_SHFT_v4_5 0x13

#define IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_BMSK_v4_5 0x3f00000

#define IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_SHFT_v4_5 0x14

#define IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_BMSK_v4_5 0x4000000

#define IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_SHFT_v4_5 0x1a

#define IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_BMSK_v4_5 0x8000000

#define IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_SHFT_v4_5 0x1b

#define IPA_ENDP_INIT_HDR_n_HDR_LEN_MSB_BMSK_v4_5 0x30000000

#define IPA_ENDP_INIT_HDR_n_HDR_LEN_MSB_SHFT_v4_5 0x1c

#define IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_MSB_BMSK_v4_5 0xc0000000

#define IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_MSB_SHFT_v4_5 0x1e



/* IPA_ENDP_INIT_HDR_EXT_n register */

#define IPA_ENDP_INIT_HDR_EXT_n_HDR_ENDIANNESS_BMSK 0x1
@@ -68,7 +89,14 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); 
#define IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_BMSK 0x3f0

#define IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_SHFT 0x4

#define IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_SHFT 0xa

#define IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_BMSK_v3_0 0x3c00

#define IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_BMSK 0x3c00

#define IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_SHFT_v4_5 0x10

#define IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_BMSK_v4_5 \

									0x30000

#define IPA_ENDP_INIT_HDR_EXT_n_HDR_OFST_PKT_SIZE_MSB_SHFT_v4_5 0x12

#define IPA_ENDP_INIT_HDR_EXT_n_HDR_OFST_PKT_SIZE_MSB_BMSK_v4_5 0xC0000

#define IPA_ENDP_INIT_HDR_EXT_n_HDR_ADDITIONAL_CONST_LEN_MSB_SHFT_v4_5 0x14

#define IPA_ENDP_INIT_HDR_EXT_n_HDR_ADDITIONAL_CONST_LEN_MSB_BMSK_v4_5 0x300000



/* IPA_ENDP_INIT_AGGR_n register */

#define IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_BMSK	0x1000000

include/linux/ipa.h

+15 −0
Original line number Diff line number Diff line
@@ -160,6 +160,11 @@ struct ipa_ep_cfg_conn_track { 
 *			correctly the length field within the header

 *			(valid only in case Hdr_Ofst_Pkt_Size_Valid=1)

 *			Valid for Output Pipes (IPA Producer)

 *			Starting IPA4.5, this field in H/W requires more bits

 *			to support larger range, but no spare bits to use.

 *			So the MSB part is done thourgh the EXT register.

 *			When accessing this register, need to access the EXT

 *			register as well.

 * @hdr_ofst_pkt_size_valid:	0: Hdr_Ofst_Pkt_Size  value is invalid, i.e., no

 *			length field within the inserted header

 *			1: Hdr_Ofst_Pkt_Size  value is valid, i.e., a
@@ -170,6 +175,11 @@ struct ipa_ep_cfg_conn_track { 
 *			header with the packet length . Assumption is that

 *			header length field size is constant and is 2Bytes

 *			Valid for Output Pipes (IPA Producer)

 *			Starting IPA4.5, this field in H/W requires more bits

 *			to support larger range, but no spare bits to use.

 *			So the MSB part is done thourgh the EXT register.

 *			When accessing this register, need to access the EXT

 *			register as well.

 * @hdr_a5_mux:	Determines whether A5 Mux header should be added to the packet.

 *			This bit is valid only when Hdr_En=01(Header Insertion)

 *			SW should set this bit for IPA-to-A5 pipes.
@@ -182,6 +192,8 @@ struct ipa_ep_cfg_conn_track { 
 * @hdr_metadata_reg_valid:	bool switch, metadata from

 *			register INIT_HDR_METADATA_n is valid.

 *			(relevant only for IPA Consumer pipes)

 *			Starting IPA4.5, this parameter is irrelevant and H/W

 *			assumes it is always valid.

 */

struct ipa_ep_cfg_hdr {

	u32  hdr_len;
@@ -213,6 +225,8 @@ struct ipa_ep_cfg_hdr { 
 * @hdr_total_len_or_pad_valid: 0-Ignore TOTAL_LEN_OR_PAD field, 1-Process

 *	TOTAL_LEN_OR_PAD field

 * @hdr_little_endian: 0-Big Endian, 1-Little Endian

 * @hdr: The header structure. Used starting IPA4.5 where part of the info

 *	at the header structure is implemented via the EXT register at the H/W

 */

struct ipa_ep_cfg_hdr_ext {

	u32 hdr_pad_to_alignment;
@@ -221,6 +235,7 @@ struct ipa_ep_cfg_hdr_ext { 
	enum hdr_total_len_or_pad_type hdr_total_len_or_pad;

	bool hdr_total_len_or_pad_valid;

	bool hdr_little_endian;

	struct ipa_ep_cfg_hdr *hdr;

};



/**