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Commit f5e127cd authored by Naveen Krishna Ch's avatar Naveen Krishna Ch Committed by Sylwester Nawrocki
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clk: samsung: exynos7: add clocks for RTC block 



Add clock support for the RTC block in Exynos7.

Signed-off-by: default avatarNaveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: default avatarAbhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
parent 6d0c8c72

Documentation/devicetree/bindings/clock/exynos7-clock.txt

+5 −0
Original line number Original line Diff line number Diff line
@@ -28,6 +28,7 @@ Required Properties for Clock Controller: 
	- "samsung,exynos7-clock-topc"

	- "samsung,exynos7-clock-topc"

	- "samsung,exynos7-clock-top0"

	- "samsung,exynos7-clock-top0"

	- "samsung,exynos7-clock-top1"

	- "samsung,exynos7-clock-top1"

	- "samsung,exynos7-clock-ccore"

	- "samsung,exynos7-clock-peric0"

	- "samsung,exynos7-clock-peric0"

	- "samsung,exynos7-clock-peric1"

	- "samsung,exynos7-clock-peric1"

	- "samsung,exynos7-clock-peris"

	- "samsung,exynos7-clock-peris"
@@ -60,6 +61,10 @@ Input clocks for top1 clock controller: 
	- dout_sclk_cc_pll

	- dout_sclk_cc_pll

	- dout_sclk_mfc_pll

	- dout_sclk_mfc_pll





Input clocks for ccore clock controller:

	- fin_pll

	- dout_aclk_ccore_133



Input clocks for peric0 clock controller:

Input clocks for peric0 clock controller:

	- fin_pll

	- fin_pll

	- dout_aclk_peric0_66

	- dout_aclk_peric0_66

drivers/clk/samsung/clk-exynos7.c

+54 −0
Original line number Original line Diff line number Diff line
@@ -29,7 +29,9 @@ 
#define AUD_PLL_CON0		0x0140

#define AUD_PLL_CON0		0x0140

#define MUX_SEL_TOPC0		0x0200

#define MUX_SEL_TOPC0		0x0200

#define MUX_SEL_TOPC1		0x0204

#define MUX_SEL_TOPC1		0x0204

#define MUX_SEL_TOPC2		0x0208

#define MUX_SEL_TOPC3		0x020C

#define MUX_SEL_TOPC3		0x020C

#define DIV_TOPC0		0x0600

#define DIV_TOPC1		0x0604

#define DIV_TOPC1		0x0604

#define DIV_TOPC3		0x060C

#define DIV_TOPC3		0x060C
@@ -78,7 +80,9 @@ static unsigned long topc_clk_regs[] __initdata = { 
	AUD_PLL_CON0,

	AUD_PLL_CON0,

	MUX_SEL_TOPC0,

	MUX_SEL_TOPC0,

	MUX_SEL_TOPC1,

	MUX_SEL_TOPC1,

	MUX_SEL_TOPC2,

	MUX_SEL_TOPC3,

	MUX_SEL_TOPC3,

	DIV_TOPC0,

	DIV_TOPC1,

	DIV_TOPC1,

	DIV_TOPC3,

	DIV_TOPC3,

};

};
@@ -101,10 +105,15 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata = { 
	MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,

	MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,

		MUX_SEL_TOPC1, 16, 1),

		MUX_SEL_TOPC1, 16, 1),





	MUX(0, "mout_aclk_ccore_133", mout_topc_group2,	MUX_SEL_TOPC2, 4, 2),



	MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),

	MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),

};

};





static struct samsung_div_clock topc_div_clks[] __initdata = {

static struct samsung_div_clock topc_div_clks[] __initdata = {

	DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",

		DIV_TOPC0, 4, 4),



	DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",

	DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",

		DIV_TOPC1, 24, 4),

		DIV_TOPC1, 24, 4),
@@ -393,6 +402,51 @@ static void __init exynos7_clk_top1_init(struct device_node *np) 
CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",

CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",

	exynos7_clk_top1_init);

	exynos7_clk_top1_init);





/* Register Offset definitions for CMU_CCORE (0x105B0000) */

#define MUX_SEL_CCORE			0x0200

#define DIV_CCORE			0x0600

#define ENABLE_ACLK_CCORE0		0x0800

#define ENABLE_ACLK_CCORE1		0x0804

#define ENABLE_PCLK_CCORE		0x0900



/*

 * List of parent clocks for Muxes in CMU_CCORE

 */

PNAME(mout_aclk_ccore_133_p)	= { "fin_pll", "dout_aclk_ccore_133" };



static unsigned long ccore_clk_regs[] __initdata = {

	MUX_SEL_CCORE,

	ENABLE_PCLK_CCORE,

};



static struct samsung_mux_clock ccore_mux_clks[] __initdata = {

	MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p,

		MUX_SEL_CCORE, 1, 1),

};



static struct samsung_gate_clock ccore_gate_clks[] __initdata = {

	GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",

		ENABLE_PCLK_CCORE, 8, 0, 0),

};



static struct samsung_cmu_info ccore_cmu_info __initdata = {

	.mux_clks		= ccore_mux_clks,

	.nr_mux_clks		= ARRAY_SIZE(ccore_mux_clks),

	.gate_clks		= ccore_gate_clks,

	.nr_gate_clks		= ARRAY_SIZE(ccore_gate_clks),

	.nr_clk_ids		= CCORE_NR_CLK,

	.clk_regs		= ccore_clk_regs,

	.nr_clk_regs		= ARRAY_SIZE(ccore_clk_regs),

};



static void __init exynos7_clk_ccore_init(struct device_node *np)

{

	samsung_cmu_register_one(np, &ccore_cmu_info);

}



CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",

	exynos7_clk_ccore_init);



/* Register Offset definitions for CMU_PERIC0 (0x13610000) */

/* Register Offset definitions for CMU_PERIC0 (0x13610000) */

#define MUX_SEL_PERIC0			0x0200

#define MUX_SEL_PERIC0			0x0200

#define ENABLE_PCLK_PERIC0		0x0900

#define ENABLE_PCLK_PERIC0		0x0900

include/dt-bindings/clock/exynos7-clk.h

+6 −1
Original line number Original line Diff line number Diff line
@@ -16,7 +16,8 @@ 
#define DOUT_SCLK_BUS1_PLL		3

#define DOUT_SCLK_BUS1_PLL		3

#define DOUT_SCLK_CC_PLL		4

#define DOUT_SCLK_CC_PLL		4

#define DOUT_SCLK_MFC_PLL		5

#define DOUT_SCLK_MFC_PLL		5

#define TOPC_NR_CLK			6

#define DOUT_ACLK_CCORE_133		6

#define TOPC_NR_CLK			7





/* TOP0 */

/* TOP0 */

#define DOUT_ACLK_PERIC1		1

#define DOUT_ACLK_PERIC1		1
@@ -38,6 +39,10 @@ 
#define CLK_SCLK_MMC0			8

#define CLK_SCLK_MMC0			8

#define TOP1_NR_CLK			9

#define TOP1_NR_CLK			9





/* CCORE */

#define PCLK_RTC			1

#define CCORE_NR_CLK			2



/* PERIC0 */

/* PERIC0 */

#define PCLK_UART0			1

#define PCLK_UART0			1

#define SCLK_UART0			2

#define SCLK_UART0			2