Merge "dts: sa8195-capture: Add cpus 1 to 7"

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

			};

		};

		CPU1: cpu@100 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x100>;

			enable-method = "psci";

			next-level-cache = <&L2_1>;

			#cooling-cells = <2>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};

			L1_I_100: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

			};

			L1_D_100: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

			};

		};

		CPU2: cpu@200 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x200>;

			enable-method = "psci";

			next-level-cache = <&L2_2>;

			#cooling-cells = <2>;

			L2_2: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};

			L1_I_200: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

			};

			L1_D_200: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

			};

		};

		CPU3: cpu@300 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x300>;

			enable-method = "psci";

			next-level-cache = <&L2_3>;

			#cooling-cells = <2>;

			L2_3: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};

			L1_I_300: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

			};

			L1_D_300: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

			};

		};

		CPU4: cpu@400 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x400>;

			enable-method = "psci";

			next-level-cache = <&L2_4>;

			#cooling-cells = <2>;

			L2_4: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};

			L1_I_400: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

			};

			L1_D_400: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

			};

		};

		CPU5: cpu@500 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x500>;

			enable-method = "psci";

			next-level-cache = <&L2_5>;

			#cooling-cells = <2>;

			L2_5: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};

			L1_I_500: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

			};

			L1_D_500: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

			};

		};

		CPU6: cpu@600 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x600>;

			enable-method = "psci";

			next-level-cache = <&L2_6>;

			#cooling-cells = <2>;

			L2_6: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};

			L1_I_600: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

			};

			L1_D_600: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

			};

		};

		CPU7: cpu@700 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x700>;

			enable-method = "psci";

			next-level-cache = <&L2_7>;

			#cooling-cells = <2>;

			L2_7: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};

			L1_I_700: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

			};

			L1_D_700: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

			};

		};

	};