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Commit f2952283 authored by Xiang Li's avatar Xiang Li
Browse files

ARM: dts: msm: Add pcie1~3 support for sa8195p 



Add PCIe1~3 lane support for sa8195p.
PCIe1 is merged with PHY of PCIe2 into a Gen3x4 lane.

Change-Id: Iba7f8fd4ce635a08a77f8a00320fe0ae57739e0a
Signed-off-by: default avatarXiang Li <lixiang@codeaurora.org>
parent fd6491fe

arch/arm64/boot/dts/qcom/sa8195p-pcie.dtsi

+948 −73

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm64/boot/dts/qcom/sdmshrike-pinctrl.dtsi

+85 −3
Original line number Diff line number Diff line
@@ -2503,6 +2503,47 @@ 
			};



			pcie1_perst_default: pcie1_perst_default {

				mux {

					pins = "gpio175";

					function = "gpio";

				};



				config {

					pins = "gpio175";

					drive-strength = <2>;

					bias-pull-down;

				};

			};



			pcie1_wake_default: pcie1_wake_default {

				mux {

					pins = "gpio177";

					function = "gpio";

				};



				config {

					pins = "gpio177";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		pcie2 {

			pcie2_clkreq_default: pcie2_clkreq_default {

				mux {

					pins = "gpio176";

					function = "pci_e2";

				};



				config {

					pins = "gpio176";

					drive-strength = <2>;

					bias-pull-up;

				};

			};



			pcie2_perst_default: pcie2_perst_default {

				mux {

					pins = "gpio102";

					function = "gpio";
@@ -2515,7 +2556,7 @@ 
				};

			};



			pcie1_wake_default: pcie1_wake_default {

			pcie2_wake_default: pcie2_wake_default {

				mux {

					pins = "gpio104";

					function = "gpio";
@@ -2529,14 +2570,55 @@ 
			};

		};



		pcie3 {

			pcie3_clkreq_default: pcie3_clkreq_default {

				mux {

					pins = "gpio179";

					function = "pci_e3";

				};



				config {

					pins = "gpio179";

					drive-strength = <2>;

					bias-pull-up;

				};

			};



			pcie3_perst_default: pcie3_perst_default {

				mux {

					pins = "gpio178";

					function = "gpio";

				};



				config {

					pins = "gpio178";

					drive-strength = <2>;

					bias-pull-down;

				};

			};



			pcie3_wake_default: pcie3_wake_default {

				mux {

					pins = "gpio56";

					function = "gpio";

				};



				config {

					pins = "gpio56";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		pcie_ep {

			pcie_ep_clkreq_default: pcie_ep_clkreq_default {

				mux {

					pins = "gpio103";

					pins = "gpio176";

					function = "pci_e1";

				};

				config {

					pins = "gpio103";

					pins = "gpio176";

					drive-strength = <2>;

					bias-disable;

				};

drivers/clk/qcom/gcc-sdmshrike.c

+28 −0
Original line number Diff line number Diff line
@@ -2895,6 +2895,19 @@ static struct clk_branch gcc_pcie_2_cfg_ahb_clk = { 
	},

};



static struct clk_branch gcc_pcie_2_clkref_clk = {

	.halt_reg = 0x8c014,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x8c014,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_2_clkref_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_pcie_2_mstr_axi_clk = {

	.halt_reg = 0x9d018,

	.halt_check = BRANCH_HALT_VOTED,
@@ -2982,6 +2995,19 @@ static struct clk_branch gcc_pcie_3_cfg_ahb_clk = { 
	},

};



static struct clk_branch gcc_pcie_3_clkref_clk = {

	.halt_reg = 0x8c018,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x8c018,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_3_clkref_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_pcie_3_mstr_axi_clk = {

	.halt_reg = 0xa3018,

	.halt_check = BRANCH_HALT_VOTED,
@@ -4870,6 +4896,7 @@ static struct clk_regmap *gcc_sdmshrike_clocks[] = { 
	[GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,

	[GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr,

	[GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,

	[GCC_PCIE_2_CLKREF_CLK] = &gcc_pcie_2_clkref_clk.clkr,

	[GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,

	[GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,

	[GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
@@ -4877,6 +4904,7 @@ static struct clk_regmap *gcc_sdmshrike_clocks[] = { 
	[GCC_PCIE_3_AUX_CLK] = &gcc_pcie_3_aux_clk.clkr,

	[GCC_PCIE_3_AUX_CLK_SRC] = &gcc_pcie_3_aux_clk_src.clkr,

	[GCC_PCIE_3_CFG_AHB_CLK] = &gcc_pcie_3_cfg_ahb_clk.clkr,

	[GCC_PCIE_3_CLKREF_CLK] = &gcc_pcie_3_clkref_clk.clkr,

	[GCC_PCIE_3_MSTR_AXI_CLK] = &gcc_pcie_3_mstr_axi_clk.clkr,

	[GCC_PCIE_3_PIPE_CLK] = &gcc_pcie_3_pipe_clk.clkr,

	[GCC_PCIE_3_SLV_AXI_CLK] = &gcc_pcie_3_slv_axi_clk.clkr,

drivers/pci/host/pci-msm.c

+30 −2
Original line number Diff line number Diff line
@@ -201,7 +201,7 @@ 
#define MSM_PCIE_MAX_VREG 4

#define MSM_PCIE_MAX_CLK 13

#define MSM_PCIE_MAX_PIPE_CLK 1

#define MAX_RC_NUM 3

#define MAX_RC_NUM 4

#define MAX_DEVICE_NUM 20

#define MAX_SHORT_BDF_NUM 16

#define PCIE_TLP_RD_SIZE 0x5
@@ -871,6 +871,13 @@ msm_pcie_reset_info[MAX_RC_NUM][MSM_PCIE_MAX_RESET] = { 
		{NULL, "pcie_phy_com_reset", false},

		{NULL, "pcie_phy_nocsr_com_phy_reset", false},

		{NULL, "pcie_2_phy_reset", false}

	},

	{

		{NULL, "pcie_3_core_reset", false},

		{NULL, "pcie_phy_reset", false},

		{NULL, "pcie_phy_com_reset", false},

		{NULL, "pcie_phy_nocsr_com_phy_reset", false},

		{NULL, "pcie_3_phy_reset", false}

	}

};
@@ -885,6 +892,9 @@ msm_pcie_pipe_reset_info[MAX_RC_NUM][MSM_PCIE_MAX_PIPE_RESET] = { 
	},

	{

		{NULL, "pcie_2_phy_pipe_reset", false}

	},

	{

		{NULL, "pcie_3_phy_pipe_reset", false}

	}

};
@@ -927,7 +937,7 @@ static struct msm_pcie_clk_info_t 
	{NULL, "pcie_2_cfg_ahb_clk", 0, false, true},

	{NULL, "pcie_2_mstr_axi_clk", 0, true, true},

	{NULL, "pcie_2_slv_axi_clk", 0, true, true},

	{NULL, "pcie_2_ldo", 0, false, true},

	{NULL, "pcie_2_ldo", 0, false, false},

	{NULL, "pcie_2_smmu_clk", 0, false, false},

	{NULL, "pcie_2_slv_q2a_axi_clk", 0, false, false},

	{NULL, "pcie_2_sleep_clk", 0, false, false},
@@ -935,6 +945,21 @@ static struct msm_pcie_clk_info_t 
	{NULL, "pcie_tbu_clk", 0, false, false},

	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},

	{NULL, "pcie_phy_aux_clk", 0, false, false}

	},

	{

	{NULL, "pcie_3_ref_clk_src", 0, false, false},

	{NULL, "pcie_3_aux_clk", 1010000, false, true},

	{NULL, "pcie_3_cfg_ahb_clk", 0, false, true},

	{NULL, "pcie_3_mstr_axi_clk", 0, true, true},

	{NULL, "pcie_3_slv_axi_clk", 0, true, true},

	{NULL, "pcie_3_ldo", 0, false, false},

	{NULL, "pcie_3_smmu_clk", 0, false, false},

	{NULL, "pcie_3_slv_q2a_axi_clk", 0, false, false},

	{NULL, "pcie_3_sleep_clk", 0, false, false},

	{NULL, "pcie_phy_refgen_clk", 0, false, false},

	{NULL, "pcie_tbu_clk", 0, false, false},

	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},

	{NULL, "pcie_phy_aux_clk", 0, false, false}

	}

};
@@ -949,6 +974,9 @@ static struct msm_pcie_clk_info_t 
	},

	{

	{NULL, "pcie_2_pipe_clk", 125000000, true, true},

	},

	{

	{NULL, "pcie_3_pipe_clk", 125000000, true, true},

	}

};

include/dt-bindings/clock/qcom,gcc-sdmshrike.h

+4 −2
Original line number Diff line number Diff line
@@ -259,8 +259,10 @@ 
#define GPLL7							242

#define GCC_PCIE_0_CLKREF_CLK					243

#define GCC_PCIE_1_CLKREF_CLK					244

#define GCC_USB3_PRIM_CLKREF_CLK				245

#define GCC_USB3_SEC_CLKREF_CLK					246

#define GCC_PCIE_2_CLKREF_CLK					245

#define GCC_PCIE_3_CLKREF_CLK					246

#define GCC_USB3_PRIM_CLKREF_CLK				247

#define GCC_USB3_SEC_CLKREF_CLK					248



#define GCC_EMAC_BCR						0

#define GCC_GPU_BCR							1