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Commit f0f5319f authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add QUPv3 entries for 2-wire UART"

parents 53344931 179bfa2a

arch/arm64/boot/dts/qcom/sa8155-vm-qupv3.dtsi

+31 −0
Original line number Diff line number Diff line
@@ -345,6 +345,21 @@ 
	};



	/* 2-wire UART */

	qupv3_se10_2uart: qcom,qup_uart@a88000 {

		compatible = "qcom,msm-geni-serial-hs";

		reg = <0xa88000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt GCC_QUPV3_WRAP1_S2_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se10_2uart_active>;

		pinctrl-1 = <&qupv3_se10_2uart_sleep>;

		interrupts = <GIC_SPI 355 0>;

		qcom,wrapper-core = <&qupv3_1>;

		status = "disabled";

	};



	/* Debug UART Instance for CDP/MTP platform */

	qupv3_se12_2uart: qcom,qup_uart@0xa90000 {
@@ -363,6 +378,22 @@ 
		status = "disabled";

	};



	qupv3_se16_2uart: qcom,qup_uart@0xa94000 {

		compatible = "qcom,msm-geni-serial-hs";

		reg = <0xa94000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt GCC_QUPV3_WRAP1_S5_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se16_2uart_active>;

		pinctrl-1 = <&qupv3_se16_2uart_sleep>;

		interrupts = <GIC_SPI 358 0>;

		qcom,wrapper-core = <&qupv3_1>;

		status = "disabled";

	};



	/* 4-wire UART */

	qupv3_se13_4uart: qcom,qup_uart@0xc8c000 {

		compatible = "qcom,msm-geni-serial-hs";

arch/arm64/boot/dts/qcom/sdmshrike-pinctrl.dtsi

+28 −0
Original line number Diff line number Diff line
@@ -4245,6 +4245,34 @@ 
			};

		};



		qupv3_se16_2uart_pins: qupv3_se16_2uart_pins {

			qupv3_se16_2uart_active: qupv3_se16_2uart_active {

				mux {

					pins = "gpio83", "gpio84";

					function = "qup16";

				};



				config {

					pins = "gpio83", "gpio84";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se16_2uart_sleep: qupv3_se16_2uart_sleep {

				mux {

					pins = "gpio83", "gpio84";

					function = "gpio";

				};



				config {

					pins = "gpio83", "gpio84";

					drive-strength = <2>;

					bias-disable;

				};

			};

		};



		/* SE 13 UART 4-Wire pin mappings */

		qupv3_se13_4uart_pins: qupv3_se13_4uart_pins {

			qupv3_se13_default_ctsrtsrx:

arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi

+56 −0
Original line number Diff line number Diff line
@@ -224,6 +224,34 @@ 
			};

		};



		qupv3_se10_2uart_pins: qupv3_se10_2uart_pins {

			qupv3_se10_2uart_active: qupv3_se10_2uart_active {

				mux {

					pins = "gpio11", "gpio12";

					function = "qup10";

				};



				config {

					pins = "gpio11", "gpio12";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se10_2uart_sleep: qupv3_se10_2uart_sleep {

				mux {

					pins = "gpio11", "gpio12";

					function = "gpio";

				};



				config {

					pins = "gpio11", "gpio12";

					drive-strength = <2>;

					bias-disable;

				};

			};

		};



		qupv3_se12_2uart_pins: qupv3_se12_2uart_pins {

			qupv3_se12_2uart_active: qupv3_se12_2uart_active {

				mux {
@@ -252,6 +280,34 @@ 
			};

		};



		qupv3_se16_2uart_pins: qupv3_se16_2uart_pins {

			qupv3_se16_2uart_active: qupv3_se16_2uart_active {

				mux {

					pins = "gpio83", "gpio84";

					function = "qup16";

				};



				config {

					pins = "gpio83", "gpio84";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se16_2uart_sleep: qupv3_se16_2uart_sleep {

				mux {

					pins = "gpio83", "gpio84";

					function = "gpio";

				};



				config {

					pins = "gpio83", "gpio84";

					drive-strength = <2>;

					bias-disable;

				};

			};

		};



		qupv3_se13_4uart_pins: qupv3_se13_4uart_pins {

			qupv3_se13_default_ctsrtsrx:

				qupv3_se13_default_ctsrtsrx {