Loading arch/arm64/boot/dts/qcom/sdmshrike.dtsi +130 −0 Original line number Diff line number Diff line Loading @@ -56,8 +56,10 @@ compatible = "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_0>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L2_0: l2-cache { Loading Loading @@ -89,8 +91,10 @@ compatible = "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_1>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L2_1: l2-cache { Loading @@ -116,8 +120,10 @@ compatible = "arm,armv8"; reg = <0x0 0x200>; enable-method = "psci"; capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_2>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L2_2: l2-cache { Loading @@ -143,8 +149,10 @@ compatible = "arm,armv8"; reg = <0x0 0x300>; enable-method = "psci"; capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_3>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L2_3: l2-cache { Loading @@ -170,8 +178,10 @@ compatible = "arm,armv8"; reg = <0x0 0x400>; enable-method = "psci"; capacity-dmips-mhz = <1740>; cache-size = <0x20000>; next-level-cache = <&L2_4>; sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; qcom,lmh-dcvs = <&lmh_dcvs1>; #cooling-cells = <2>; L2_4: l2-cache { Loading @@ -197,8 +207,10 @@ compatible = "arm,armv8"; reg = <0x0 0x500>; enable-method = "psci"; capacity-dmips-mhz = <1740>; cache-size = <0x20000>; next-level-cache = <&L2_5>; sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; qcom,lmh-dcvs = <&lmh_dcvs1>; #cooling-cells = <2>; L2_5: l2-cache { Loading @@ -224,8 +236,10 @@ compatible = "arm,armv8"; reg = <0x0 0x600>; enable-method = "psci"; capacity-dmips-mhz = <1740>; cache-size = <0x20000>; next-level-cache = <&L2_6>; sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; qcom,lmh-dcvs = <&lmh_dcvs1>; #cooling-cells = <2>; L2_6: l2-cache { Loading @@ -251,8 +265,10 @@ compatible = "arm,armv8"; reg = <0x0 0x700>; enable-method = "psci"; capacity-dmips-mhz = <1740>; cache-size = <0x20000>; next-level-cache = <&L2_7>; sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; qcom,lmh-dcvs = <&lmh_dcvs1>; #cooling-cells = <2>; L2_7: l2-cache { Loading Loading @@ -317,6 +333,120 @@ }; }; energy_costs: energy-costs { compatible = "sched-energy"; CPU_COST_0: core-cost0 { busy-cost-data = < 300000 24 403200 25 499200 27 576000 29 672000 33 768000 37 844800 42 940800 47 1036800 54 1113600 59 1209600 66 1305600 73 1382400 79 1478400 88 1555200 96 1632000 105 1708800 115 1785600 128 >; idle-cost-data = < 18 14 12 >; }; CPU_COST_1: core-cost1 { busy-cost-data = < 825600 227 940800 262 1056000 302 1171200 348 1286400 398 1401600 451 1497600 498 1612800 556 1708800 606 1804800 655 1920000 716 2016000 766 2131200 826 2227200 878 2323200 933 2419200 992 2534400 1075 2649600 1179 2745600 1288 2841600 1427 2956800 1670 >; idle-cost-data = < 110 90 70 >; }; CLUSTER_COST_0: cluster-cost0 { busy-cost-data = < 300000 3 403200 4 499200 4 576000 4 672000 5 768000 5 844800 6 940800 7 1036800 8 1113600 9 1209600 10 1305600 11 1382400 12 1478400 13 1555200 14 1632000 15 1708800 16 1785600 17 >; idle-cost-data = < 3 2 1 >; }; CLUSTER_COST_1: cluster-cost1 { busy-cost-data = < 825600 30 940800 33 1056000 36 1171200 39 1286400 42 1401600 46 1497600 49 1612800 55 1708800 67 1804800 77 1920000 87 2016000 100 2131200 110 2227200 120 2323200 128 2419200 135 2534400 140 2649600 147 2745600 160 2841600 180 2956800 197 >; idle-cost-data = < 3 2 1 >; }; }; /* energy-costs */ cpuss_dump { compatible = "qcom,cpuss-dump"; Loading Loading
arch/arm64/boot/dts/qcom/sdmshrike.dtsi +130 −0 Original line number Diff line number Diff line Loading @@ -56,8 +56,10 @@ compatible = "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_0>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L2_0: l2-cache { Loading Loading @@ -89,8 +91,10 @@ compatible = "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_1>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L2_1: l2-cache { Loading @@ -116,8 +120,10 @@ compatible = "arm,armv8"; reg = <0x0 0x200>; enable-method = "psci"; capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_2>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L2_2: l2-cache { Loading @@ -143,8 +149,10 @@ compatible = "arm,armv8"; reg = <0x0 0x300>; enable-method = "psci"; capacity-dmips-mhz = <1024>; cache-size = <0x8000>; next-level-cache = <&L2_3>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L2_3: l2-cache { Loading @@ -170,8 +178,10 @@ compatible = "arm,armv8"; reg = <0x0 0x400>; enable-method = "psci"; capacity-dmips-mhz = <1740>; cache-size = <0x20000>; next-level-cache = <&L2_4>; sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; qcom,lmh-dcvs = <&lmh_dcvs1>; #cooling-cells = <2>; L2_4: l2-cache { Loading @@ -197,8 +207,10 @@ compatible = "arm,armv8"; reg = <0x0 0x500>; enable-method = "psci"; capacity-dmips-mhz = <1740>; cache-size = <0x20000>; next-level-cache = <&L2_5>; sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; qcom,lmh-dcvs = <&lmh_dcvs1>; #cooling-cells = <2>; L2_5: l2-cache { Loading @@ -224,8 +236,10 @@ compatible = "arm,armv8"; reg = <0x0 0x600>; enable-method = "psci"; capacity-dmips-mhz = <1740>; cache-size = <0x20000>; next-level-cache = <&L2_6>; sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; qcom,lmh-dcvs = <&lmh_dcvs1>; #cooling-cells = <2>; L2_6: l2-cache { Loading @@ -251,8 +265,10 @@ compatible = "arm,armv8"; reg = <0x0 0x700>; enable-method = "psci"; capacity-dmips-mhz = <1740>; cache-size = <0x20000>; next-level-cache = <&L2_7>; sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; qcom,lmh-dcvs = <&lmh_dcvs1>; #cooling-cells = <2>; L2_7: l2-cache { Loading Loading @@ -317,6 +333,120 @@ }; }; energy_costs: energy-costs { compatible = "sched-energy"; CPU_COST_0: core-cost0 { busy-cost-data = < 300000 24 403200 25 499200 27 576000 29 672000 33 768000 37 844800 42 940800 47 1036800 54 1113600 59 1209600 66 1305600 73 1382400 79 1478400 88 1555200 96 1632000 105 1708800 115 1785600 128 >; idle-cost-data = < 18 14 12 >; }; CPU_COST_1: core-cost1 { busy-cost-data = < 825600 227 940800 262 1056000 302 1171200 348 1286400 398 1401600 451 1497600 498 1612800 556 1708800 606 1804800 655 1920000 716 2016000 766 2131200 826 2227200 878 2323200 933 2419200 992 2534400 1075 2649600 1179 2745600 1288 2841600 1427 2956800 1670 >; idle-cost-data = < 110 90 70 >; }; CLUSTER_COST_0: cluster-cost0 { busy-cost-data = < 300000 3 403200 4 499200 4 576000 4 672000 5 768000 5 844800 6 940800 7 1036800 8 1113600 9 1209600 10 1305600 11 1382400 12 1478400 13 1555200 14 1632000 15 1708800 16 1785600 17 >; idle-cost-data = < 3 2 1 >; }; CLUSTER_COST_1: cluster-cost1 { busy-cost-data = < 825600 30 940800 33 1056000 36 1171200 39 1286400 42 1401600 46 1497600 49 1612800 55 1708800 67 1804800 77 1920000 87 2016000 100 2131200 110 2227200 120 2323200 128 2419200 135 2534400 140 2649600 147 2745600 160 2841600 180 2956800 197 >; idle-cost-data = < 3 2 1 >; }; }; /* energy-costs */ cpuss_dump { compatible = "qcom,cpuss-dump"; Loading