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Commit efeff568 authored by Werner Almesberger's avatar Werner Almesberger Committed by Ben Dooks
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[ARM] S3C64XX: Fix s3c64xx_setrate_clksrc 



Some of the rate selection logic in s3c64xx_setrate_clksrc uses what
appears to be parent clock selection logic. This patch corrects it.

I also added a check for overly large dividers to prevent them from
changing unrelated clocks.

Signed-off-by: default avatarWerner Almesberger <werner@openmoko.org>
Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
parent fdca9bf2

arch/arm/plat-s3c64xx/s3c6400-clock.c

+4 −2
Original line number Original line Diff line number Diff line
@@ -239,10 +239,12 @@ static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate) 




	rate = clk_round_rate(clk, rate);

	rate = clk_round_rate(clk, rate);

	div = clk_get_rate(clk->parent) / rate;

	div = clk_get_rate(clk->parent) / rate;

	if (div > 16)

		return -EINVAL;





	val = __raw_readl(reg);

	val = __raw_readl(reg);

	val &= ~sclk->mask;

	val &= ~(0xf << sclk->shift);

	val |= (rate - 1) << sclk->shift;

	val |= (div - 1) << sclk->shift;

	__raw_writel(val, reg);

	__raw_writel(val, reg);





	return 0;

	return 0;