Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit eeb2487d authored by Monk Liu's avatar Monk Liu Committed by Alex Deucher
Browse files

drm/amdgpu:fix missing programing critical registers 



those MC_VM registers won't be programed by VBIOS in VF
so driver is responsible to programe them.

Signed-off-by: default avatarMonk Liu <Monk.Liu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5846e355

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

+9 −0
Original line number Diff line number Diff line
@@ -53,6 +53,15 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) 
				mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),

				(u32)(value >> 44));



	if (amdgpu_sriov_vf(adev)) {

		/* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so

		vbios post doesn't program them, for SRIOV driver need to program them */

		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE),

				adev->mc.vram_start >> 24);

		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP),

				adev->mc.vram_end >> 24);

	}



	/* Disable AGP. */

	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BASE), 0);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_TOP), 0);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+3 −1
Original line number Diff line number Diff line
@@ -382,7 +382,9 @@ static int gmc_v9_0_late_init(void *handle) 
static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,

					struct amdgpu_mc *mc)

{

	u64 base = mmhub_v1_0_get_fb_location(adev);

	u64 base = 0;

	if (!amdgpu_sriov_vf(adev))

		base = mmhub_v1_0_get_fb_location(adev);

	amdgpu_vram_location(adev, &adev->mc, base);

	adev->mc.gtt_base_align = 0;

	amdgpu_gtt_location(adev, mc);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+9 −0
Original line number Diff line number Diff line
@@ -67,6 +67,15 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) 
				mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),

				(u32)(value >> 44));



	if (amdgpu_sriov_vf(adev)) {

		/* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so

		vbios post doesn't program them, for SRIOV driver need to program them */

		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE),

			adev->mc.vram_start >> 24);

		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP),

			adev->mc.vram_end >> 24);

	}



	/* Disable AGP. */

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_BASE), 0);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_TOP), 0);