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Commit ea86e2d2 authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

clk: qcom: gcc-sm8150: Pull in changes to the GCC clock frequency plan 



There have been updates to the frequency plan for peripheral
clocks. Pull these into the clock driver.

Change-Id: Ifb206477913aebddbc09f380631d5b83af3530dd
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent dd5080ee

drivers/clk/qcom/gcc-sm8150.c

+15 −126
Original line number Diff line number Diff line
@@ -51,10 +51,7 @@ enum { 
	P_CORE_BI_PLL_TEST_SE,

	P_GPLL0_OUT_EVEN,

	P_GPLL0_OUT_MAIN,

	P_GPLL1_OUT_MAIN,

	P_GPLL2_OUT_MAIN,

	P_GPLL4_OUT_MAIN,

	P_GPLL5_OUT_MAIN,

	P_GPLL7_OUT_MAIN,

	P_GPLL9_OUT_MAIN,

	P_SLEEP_CLK,
@@ -131,28 +128,6 @@ static const char * const gcc_parent_names_4[] = { 
};



static const struct parent_map gcc_parent_map_5[] = {

	{ P_BI_TCXO, 0 },

	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_GPLL2_OUT_MAIN, 2 },

	{ P_GPLL5_OUT_MAIN, 3 },

	{ P_GPLL1_OUT_MAIN, 4 },

	{ P_GPLL4_OUT_MAIN, 5 },

	{ P_GPLL0_OUT_EVEN, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const char * const gcc_parent_names_5[] = {

	"bi_tcxo",

	"gpll0",

	"gpll2",

	"gpll5",

	"gpll1",

	"gpll4",

	"gpll0_out_even",

	"core_bi_pll_test_se",

};



static const struct parent_map gcc_parent_map_6[] = {

	{ P_BI_TCXO, 0 },

	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_GPLL7_OUT_MAIN, 3 },
@@ -160,7 +135,7 @@ static const struct parent_map gcc_parent_map_6[] = { 
	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const char * const gcc_parent_names_6[] = {

static const char * const gcc_parent_names_5[] = {

	"bi_tcxo",

	"gpll0",

	"gpll7",
@@ -168,7 +143,7 @@ static const char * const gcc_parent_names_6[] = { 
	"core_bi_pll_test_se",

};



static const struct parent_map gcc_parent_map_7[] = {

static const struct parent_map gcc_parent_map_6[] = {

	{ P_BI_TCXO, 0 },

	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_GPLL9_OUT_MAIN, 2 },
@@ -177,7 +152,7 @@ static const struct parent_map gcc_parent_map_7[] = { 
	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const char * const gcc_parent_names_7[] = {

static const char * const gcc_parent_names_6[] = {

	"bi_tcxo",

	"gpll0",

	"gpll9",
@@ -186,7 +161,7 @@ static const char * const gcc_parent_names_7[] = { 
	"core_bi_pll_test_se",

};



static const struct parent_map gcc_parent_map_8[] = {

static const struct parent_map gcc_parent_map_7[] = {

	{ P_BI_TCXO, 0 },

	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_AUD_REF_CLK, 2 },
@@ -194,7 +169,7 @@ static const struct parent_map gcc_parent_map_8[] = { 
	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const char * const gcc_parent_names_8[] = {

static const char * const gcc_parent_names_7[] = {

	"bi_tcxo",

	"gpll0",

	"aud_ref_clk",
@@ -294,54 +269,6 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = { 
	},

};



static struct clk_alpha_pll gpll1 = {

	.offset = 0x1000,

	.vco_table = trion_vco,

	.num_vco = ARRAY_SIZE(trion_vco),

	.type = TRION_PLL,

	.clkr = {

		.enable_reg = 0x52000,

		.enable_mask = BIT(1),

		.hw.init = &(struct clk_init_data){

			.name = "gpll1",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.ops = &clk_trion_fixed_pll_ops,

			.vdd_class = &vdd_cx,

			.num_rate_max = VDD_NUM,

			.rate_max = (unsigned long[VDD_NUM]) {

				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1600000000,

				[VDD_NOMINAL] = 2000000000},

		},

	},

};



static struct clk_alpha_pll gpll4 = {

	.offset = 0x76000,

	.vco_table = trion_vco,

	.num_vco = ARRAY_SIZE(trion_vco),

	.type = TRION_PLL,

	.clkr = {

		.enable_reg = 0x52000,

		.enable_mask = BIT(4),

		.hw.init = &(struct clk_init_data){

			.name = "gpll4",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.ops = &clk_trion_fixed_pll_ops,

			.vdd_class = &vdd_cx,

			.num_rate_max = VDD_NUM,

			.rate_max = (unsigned long[VDD_NUM]) {

				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1600000000,

				[VDD_NOMINAL] = 2000000000},

		},

	},

};



static struct clk_alpha_pll gpll7 = {

	.offset = 0x1a000,

	.vco_table = trion_vco,
@@ -430,11 +357,11 @@ static struct clk_rcg2 gcc_emac_ptp_clk_src = { 
	.cmd_rcgr = 0x6038,

	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = gcc_parent_map_6,

	.parent_map = gcc_parent_map_5,

	.freq_tbl = ftbl_gcc_emac_ptp_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_emac_ptp_clk_src",

		.parent_names = gcc_parent_names_6,

		.parent_names = gcc_parent_names_5,

		.num_parents = 5,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,
@@ -463,11 +390,11 @@ static struct clk_rcg2 gcc_emac_rgmii_clk_src = { 
	.cmd_rcgr = 0x601c,

	.mnd_width = 8,

	.hid_width = 5,

	.parent_map = gcc_parent_map_6,

	.parent_map = gcc_parent_map_5,

	.freq_tbl = ftbl_gcc_emac_rgmii_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_emac_rgmii_clk_src",

		.parent_names = gcc_parent_names_6,

		.parent_names = gcc_parent_names_5,

		.num_parents = 5,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,
@@ -556,41 +483,6 @@ static struct clk_rcg2 gcc_gp3_clk_src = { 
	},

};



static const struct freq_tbl ftbl_gcc_npu_axi_clk_src[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),

	F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),

	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),

	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),

	F(403000000, P_GPLL4_OUT_MAIN, 2, 0, 0),

	F(533000000, P_GPLL1_OUT_MAIN, 2, 0, 0),

	{ }

};



static struct clk_rcg2 gcc_npu_axi_clk_src = {

	.cmd_rcgr = 0x4d014,

	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = gcc_parent_map_5,

	.freq_tbl = ftbl_gcc_npu_axi_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_npu_axi_clk_src",

		.parent_names = gcc_parent_names_5,

		.num_parents = 8,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_cx,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 60000000,

			[VDD_LOWER] = 150000000,

			[VDD_LOW] = 200000000,

			[VDD_LOW_L1] = 300000000,

			[VDD_NOMINAL] = 403000000,

			[VDD_HIGH] = 533000000},

	},

};



static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {

	F(9600000, P_BI_TCXO, 2, 0, 0),

	F(19200000, P_BI_TCXO, 1, 0, 0),
@@ -1187,7 +1079,7 @@ static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 
	F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),

	F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),

	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),

	F(201600000, P_GPLL9_OUT_MAIN, 4, 0, 0),

	F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),

	{ }

};
@@ -1195,11 +1087,11 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 
	.cmd_rcgr = 0x1400c,

	.mnd_width = 8,

	.hid_width = 5,

	.parent_map = gcc_parent_map_7,

	.parent_map = gcc_parent_map_6,

	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_sdcc2_apps_clk_src",

		.parent_names = gcc_parent_names_7,

		.parent_names = gcc_parent_names_6,

		.num_parents = 6,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,
@@ -1208,7 +1100,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 
		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 19200000,

			[VDD_LOW] = 100000000,

			[VDD_LOW_L1] = 201600000},

			[VDD_LOW_L1] = 202000000},

	},

};
@@ -1252,11 +1144,11 @@ static struct clk_rcg2 gcc_tsif_ref_clk_src = { 
	.cmd_rcgr = 0x36010,

	.mnd_width = 8,

	.hid_width = 5,

	.parent_map = gcc_parent_map_8,

	.parent_map = gcc_parent_map_7,

	.freq_tbl = ftbl_gcc_tsif_ref_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_tsif_ref_clk_src",

		.parent_names = gcc_parent_names_8,

		.parent_names = gcc_parent_names_7,

		.num_parents = 5,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,
@@ -4066,7 +3958,6 @@ static struct clk_regmap *gcc_sm8150_clocks[] = { 
	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,

	[GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr,

	[GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,

	[GCC_NPU_AXI_CLK_SRC] = &gcc_npu_axi_clk_src.clkr,

	[GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,

	[GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,

	[GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
@@ -4231,8 +4122,6 @@ static struct clk_regmap *gcc_sm8150_clocks[] = { 
	[GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,

	[GPLL0] = &gpll0.clkr,

	[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,

	[GPLL1] = &gpll1.clkr,

	[GPLL4] = &gpll4.clkr,

	[GPLL7] = &gpll7.clkr,

	[GPLL9] = &gpll9.clkr,

};

include/dt-bindings/clock/qcom,gcc-sm8150.h

+157 −160
Original line number Diff line number Diff line
@@ -59,166 +59,163 @@ 
#define GCC_GPU_SNOC_DVM_GFX_CLK				41

#define GCC_NPU_AT_CLK						42

#define GCC_NPU_AXI_CLK						43

#define GCC_NPU_AXI_CLK_SRC					44

#define GCC_NPU_CFG_AHB_CLK					45

#define GCC_NPU_GPLL0_CLK_SRC					46

#define GCC_NPU_GPLL0_DIV_CLK_SRC				47

#define GCC_NPU_TRIG_CLK					48

#define GCC_PCIE0_PHY_REFGEN_CLK				49

#define GCC_PCIE1_PHY_REFGEN_CLK				50

#define GCC_PCIE_0_AUX_CLK					51

#define GCC_PCIE_0_AUX_CLK_SRC					52

#define GCC_PCIE_0_CFG_AHB_CLK					53

#define GCC_PCIE_0_CLKREF_CLK					54

#define GCC_PCIE_0_MSTR_AXI_CLK					55

#define GCC_PCIE_0_PIPE_CLK					56

#define GCC_PCIE_0_SLV_AXI_CLK					57

#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				58

#define GCC_PCIE_1_AUX_CLK					59

#define GCC_PCIE_1_AUX_CLK_SRC					60

#define GCC_PCIE_1_CFG_AHB_CLK					61

#define GCC_PCIE_1_CLKREF_CLK					62

#define GCC_PCIE_1_MSTR_AXI_CLK					63

#define GCC_PCIE_1_PIPE_CLK					64

#define GCC_PCIE_1_SLV_AXI_CLK					65

#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				66

#define GCC_PCIE_PHY_AUX_CLK					67

#define GCC_PCIE_PHY_REFGEN_CLK_SRC				68

#define GCC_PDM2_CLK						69

#define GCC_PDM2_CLK_SRC					70

#define GCC_PDM_AHB_CLK						71

#define GCC_PDM_XO4_CLK						72

#define GCC_PRNG_AHB_CLK					73

#define GCC_QMIP_CAMERA_NRT_AHB_CLK				74

#define GCC_QMIP_CAMERA_RT_AHB_CLK				75

#define GCC_QMIP_DISP_AHB_CLK					76

#define GCC_QMIP_VIDEO_CVP_AHB_CLK				77

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				78

#define GCC_QSPI_CNOC_PERIPH_AHB_CLK				79

#define GCC_QSPI_CORE_CLK					80

#define GCC_QSPI_CORE_CLK_SRC					81

#define GCC_QUPV3_WRAP0_S0_CLK					82

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				83

#define GCC_QUPV3_WRAP0_S1_CLK					84

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				85

#define GCC_QUPV3_WRAP0_S2_CLK					86

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				87

#define GCC_QUPV3_WRAP0_S3_CLK					88

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				89

#define GCC_QUPV3_WRAP0_S4_CLK					90

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				91

#define GCC_QUPV3_WRAP0_S5_CLK					92

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				93

#define GCC_QUPV3_WRAP0_S6_CLK					94

#define GCC_QUPV3_WRAP0_S6_CLK_SRC				95

#define GCC_QUPV3_WRAP0_S7_CLK					96

#define GCC_QUPV3_WRAP0_S7_CLK_SRC				97

#define GCC_QUPV3_WRAP1_S0_CLK					98

#define GCC_QUPV3_WRAP1_S0_CLK_SRC				99

#define GCC_QUPV3_WRAP1_S1_CLK					100

#define GCC_QUPV3_WRAP1_S1_CLK_SRC				101

#define GCC_QUPV3_WRAP1_S2_CLK					102

#define GCC_QUPV3_WRAP1_S2_CLK_SRC				103

#define GCC_QUPV3_WRAP1_S3_CLK					104

#define GCC_QUPV3_WRAP1_S3_CLK_SRC				105

#define GCC_QUPV3_WRAP1_S4_CLK					106

#define GCC_QUPV3_WRAP1_S4_CLK_SRC				107

#define GCC_QUPV3_WRAP1_S5_CLK					108

#define GCC_QUPV3_WRAP1_S5_CLK_SRC				109

#define GCC_QUPV3_WRAP2_S0_CLK					110

#define GCC_QUPV3_WRAP2_S0_CLK_SRC				111

#define GCC_QUPV3_WRAP2_S1_CLK					112

#define GCC_QUPV3_WRAP2_S1_CLK_SRC				113

#define GCC_QUPV3_WRAP2_S2_CLK					114

#define GCC_QUPV3_WRAP2_S2_CLK_SRC				115

#define GCC_QUPV3_WRAP2_S3_CLK					116

#define GCC_QUPV3_WRAP2_S3_CLK_SRC				117

#define GCC_QUPV3_WRAP2_S4_CLK					118

#define GCC_QUPV3_WRAP2_S4_CLK_SRC				119

#define GCC_QUPV3_WRAP2_S5_CLK					120

#define GCC_QUPV3_WRAP2_S5_CLK_SRC				121

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				122

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				123

#define GCC_QUPV3_WRAP_1_M_AHB_CLK				124

#define GCC_QUPV3_WRAP_1_S_AHB_CLK				125

#define GCC_QUPV3_WRAP_2_M_AHB_CLK				126

#define GCC_QUPV3_WRAP_2_S_AHB_CLK				127

#define GCC_SDCC2_AHB_CLK					128

#define GCC_SDCC2_APPS_CLK					129

#define GCC_SDCC2_APPS_CLK_SRC					130

#define GCC_SDCC4_AHB_CLK					131

#define GCC_SDCC4_APPS_CLK					132

#define GCC_SDCC4_APPS_CLK_SRC					133

#define GCC_SYS_NOC_CPUSS_AHB_CLK				134

#define GCC_TSIF_AHB_CLK					135

#define GCC_TSIF_INACTIVITY_TIMERS_CLK				136

#define GCC_TSIF_REF_CLK					137

#define GCC_TSIF_REF_CLK_SRC					138

#define GCC_UFS_CARD_AHB_CLK					139

#define GCC_UFS_CARD_AXI_CLK					140

#define GCC_UFS_CARD_AXI_CLK_SRC				141

#define GCC_UFS_CARD_AXI_HW_CTL_CLK				142

#define GCC_UFS_CARD_CLKREF_CLK					143

#define GCC_UFS_CARD_ICE_CORE_CLK				144

#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				145

#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK			146

#define GCC_UFS_CARD_PHY_AUX_CLK				147

#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				148

#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK				149

#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				150

#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				151

#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				152

#define GCC_UFS_CARD_UNIPRO_CORE_CLK				153

#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			154

#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK			155

#define GCC_UFS_MEM_CLKREF_CLK					156

#define GCC_UFS_PHY_AHB_CLK					157

#define GCC_UFS_PHY_AXI_CLK					158

#define GCC_UFS_PHY_AXI_CLK_SRC					159

#define GCC_UFS_PHY_AXI_HW_CTL_CLK				160

#define GCC_UFS_PHY_ICE_CORE_CLK				161

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				162

#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK				163

#define GCC_UFS_PHY_PHY_AUX_CLK					164

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				165

#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				166

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				167

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				168

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				169

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				170

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				171

#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			172

#define GCC_USB30_PRIM_MASTER_CLK				173

#define GCC_USB30_PRIM_MASTER_CLK_SRC				174

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				175

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			176

#define GCC_USB30_PRIM_SLEEP_CLK				177

#define GCC_USB30_SEC_MASTER_CLK				178

#define GCC_USB30_SEC_MASTER_CLK_SRC				179

#define GCC_USB30_SEC_MOCK_UTMI_CLK				180

#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				181

#define GCC_USB30_SEC_SLEEP_CLK					182

#define GCC_USB3_PRIM_CLKREF_CLK				183

#define GCC_USB3_PRIM_PHY_AUX_CLK				184

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				185

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				186

#define GCC_USB3_PRIM_PHY_PIPE_CLK				187

#define GCC_USB3_SEC_CLKREF_CLK					188

#define GCC_USB3_SEC_PHY_AUX_CLK				189

#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				190

#define GCC_USB3_SEC_PHY_COM_AUX_CLK				191

#define GCC_USB3_SEC_PHY_PIPE_CLK				192

#define GCC_VIDEO_AHB_CLK					193

#define GCC_VIDEO_AXI0_CLK					194

#define GCC_VIDEO_AXI1_CLK					195

#define GCC_VIDEO_AXIC_CLK					196

#define GCC_VIDEO_XO_CLK					197

#define GPLL0							198

#define GPLL0_OUT_EVEN						199

#define GPLL1							200

#define GPLL4							201

#define GPLL7							202

#define GPLL9							203

#define GCC_NPU_CFG_AHB_CLK					44

#define GCC_NPU_GPLL0_CLK_SRC					45

#define GCC_NPU_GPLL0_DIV_CLK_SRC				46

#define GCC_NPU_TRIG_CLK					47

#define GCC_PCIE0_PHY_REFGEN_CLK				48

#define GCC_PCIE1_PHY_REFGEN_CLK				49

#define GCC_PCIE_0_AUX_CLK					50

#define GCC_PCIE_0_AUX_CLK_SRC					51

#define GCC_PCIE_0_CFG_AHB_CLK					52

#define GCC_PCIE_0_CLKREF_CLK					53

#define GCC_PCIE_0_MSTR_AXI_CLK					54

#define GCC_PCIE_0_PIPE_CLK					55

#define GCC_PCIE_0_SLV_AXI_CLK					56

#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				57

#define GCC_PCIE_1_AUX_CLK					58

#define GCC_PCIE_1_AUX_CLK_SRC					59

#define GCC_PCIE_1_CFG_AHB_CLK					60

#define GCC_PCIE_1_CLKREF_CLK					61

#define GCC_PCIE_1_MSTR_AXI_CLK					62

#define GCC_PCIE_1_PIPE_CLK					63

#define GCC_PCIE_1_SLV_AXI_CLK					64

#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				65

#define GCC_PCIE_PHY_AUX_CLK					66

#define GCC_PCIE_PHY_REFGEN_CLK_SRC				67

#define GCC_PDM2_CLK						68

#define GCC_PDM2_CLK_SRC					69

#define GCC_PDM_AHB_CLK						70

#define GCC_PDM_XO4_CLK						71

#define GCC_PRNG_AHB_CLK					72

#define GCC_QMIP_CAMERA_NRT_AHB_CLK				73

#define GCC_QMIP_CAMERA_RT_AHB_CLK				74

#define GCC_QMIP_DISP_AHB_CLK					75

#define GCC_QMIP_VIDEO_CVP_AHB_CLK				76

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				77

#define GCC_QSPI_CNOC_PERIPH_AHB_CLK				78

#define GCC_QSPI_CORE_CLK					79

#define GCC_QSPI_CORE_CLK_SRC					80

#define GCC_QUPV3_WRAP0_S0_CLK					81

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				82

#define GCC_QUPV3_WRAP0_S1_CLK					83

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				84

#define GCC_QUPV3_WRAP0_S2_CLK					85

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				86

#define GCC_QUPV3_WRAP0_S3_CLK					87

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				88

#define GCC_QUPV3_WRAP0_S4_CLK					89

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				90

#define GCC_QUPV3_WRAP0_S5_CLK					91

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				92

#define GCC_QUPV3_WRAP0_S6_CLK					93

#define GCC_QUPV3_WRAP0_S6_CLK_SRC				94

#define GCC_QUPV3_WRAP0_S7_CLK					95

#define GCC_QUPV3_WRAP0_S7_CLK_SRC				96

#define GCC_QUPV3_WRAP1_S0_CLK					97

#define GCC_QUPV3_WRAP1_S0_CLK_SRC				98

#define GCC_QUPV3_WRAP1_S1_CLK					99

#define GCC_QUPV3_WRAP1_S1_CLK_SRC				100

#define GCC_QUPV3_WRAP1_S2_CLK					101

#define GCC_QUPV3_WRAP1_S2_CLK_SRC				102

#define GCC_QUPV3_WRAP1_S3_CLK					103

#define GCC_QUPV3_WRAP1_S3_CLK_SRC				104

#define GCC_QUPV3_WRAP1_S4_CLK					105

#define GCC_QUPV3_WRAP1_S4_CLK_SRC				106

#define GCC_QUPV3_WRAP1_S5_CLK					107

#define GCC_QUPV3_WRAP1_S5_CLK_SRC				108

#define GCC_QUPV3_WRAP2_S0_CLK					109

#define GCC_QUPV3_WRAP2_S0_CLK_SRC				110

#define GCC_QUPV3_WRAP2_S1_CLK					111

#define GCC_QUPV3_WRAP2_S1_CLK_SRC				112

#define GCC_QUPV3_WRAP2_S2_CLK					113

#define GCC_QUPV3_WRAP2_S2_CLK_SRC				114

#define GCC_QUPV3_WRAP2_S3_CLK					115

#define GCC_QUPV3_WRAP2_S3_CLK_SRC				116

#define GCC_QUPV3_WRAP2_S4_CLK					117

#define GCC_QUPV3_WRAP2_S4_CLK_SRC				118

#define GCC_QUPV3_WRAP2_S5_CLK					119

#define GCC_QUPV3_WRAP2_S5_CLK_SRC				120

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				121

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				122

#define GCC_QUPV3_WRAP_1_M_AHB_CLK				123

#define GCC_QUPV3_WRAP_1_S_AHB_CLK				124

#define GCC_QUPV3_WRAP_2_M_AHB_CLK				125

#define GCC_QUPV3_WRAP_2_S_AHB_CLK				126

#define GCC_SDCC2_AHB_CLK					127

#define GCC_SDCC2_APPS_CLK					128

#define GCC_SDCC2_APPS_CLK_SRC					129

#define GCC_SDCC4_AHB_CLK					130

#define GCC_SDCC4_APPS_CLK					131

#define GCC_SDCC4_APPS_CLK_SRC					132

#define GCC_SYS_NOC_CPUSS_AHB_CLK				133

#define GCC_TSIF_AHB_CLK					134

#define GCC_TSIF_INACTIVITY_TIMERS_CLK				135

#define GCC_TSIF_REF_CLK					136

#define GCC_TSIF_REF_CLK_SRC					137

#define GCC_UFS_CARD_AHB_CLK					138

#define GCC_UFS_CARD_AXI_CLK					139

#define GCC_UFS_CARD_AXI_CLK_SRC				140

#define GCC_UFS_CARD_AXI_HW_CTL_CLK				141

#define GCC_UFS_CARD_CLKREF_CLK					142

#define GCC_UFS_CARD_ICE_CORE_CLK				143

#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				144

#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK			145

#define GCC_UFS_CARD_PHY_AUX_CLK				146

#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				147

#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK				148

#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				149

#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				150

#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				151

#define GCC_UFS_CARD_UNIPRO_CORE_CLK				152

#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			153

#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK			154

#define GCC_UFS_MEM_CLKREF_CLK					155

#define GCC_UFS_PHY_AHB_CLK					156

#define GCC_UFS_PHY_AXI_CLK					157

#define GCC_UFS_PHY_AXI_CLK_SRC					158

#define GCC_UFS_PHY_AXI_HW_CTL_CLK				159

#define GCC_UFS_PHY_ICE_CORE_CLK				160

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				161

#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK				162

#define GCC_UFS_PHY_PHY_AUX_CLK					163

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				164

#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				165

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				166

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				167

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				168

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				169

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				170

#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			171

#define GCC_USB30_PRIM_MASTER_CLK				172

#define GCC_USB30_PRIM_MASTER_CLK_SRC				173

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				174

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			175

#define GCC_USB30_PRIM_SLEEP_CLK				176

#define GCC_USB30_SEC_MASTER_CLK				177

#define GCC_USB30_SEC_MASTER_CLK_SRC				178

#define GCC_USB30_SEC_MOCK_UTMI_CLK				179

#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				180

#define GCC_USB30_SEC_SLEEP_CLK					181

#define GCC_USB3_PRIM_CLKREF_CLK				182

#define GCC_USB3_PRIM_PHY_AUX_CLK				183

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				184

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				185

#define GCC_USB3_PRIM_PHY_PIPE_CLK				186

#define GCC_USB3_SEC_CLKREF_CLK					187

#define GCC_USB3_SEC_PHY_AUX_CLK				188

#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				189

#define GCC_USB3_SEC_PHY_COM_AUX_CLK				190

#define GCC_USB3_SEC_PHY_PIPE_CLK				191

#define GCC_VIDEO_AHB_CLK					192

#define GCC_VIDEO_AXI0_CLK					193

#define GCC_VIDEO_AXI1_CLK					194

#define GCC_VIDEO_AXIC_CLK					195

#define GCC_VIDEO_XO_CLK					196

#define GPLL0							197

#define GPLL0_OUT_EVEN						198

#define GPLL7							199

#define GPLL9							200



/* Reset clocks */

#define GCC_EMAC_BCR						0