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Commit ea0128d1 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/dsi-staging: Add C-PHY support for phy ver 3.0"

parents 7e2a2f0c db18ff12

Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt

+1 −0
Original line number Diff line number Diff line
@@ -497,6 +497,7 @@ Optional properties: 
- qcom,panel-ack-disabled: A boolean property to indicate, whether we need to wait for any ACK from the panel

			   for any commands that we send.

- qcom,mdss-dsi-force-clock-lane-hs:	Boolean to force dsi clock lanes to HS mode always.

- qcom,panel-cphy-mode:			Boolean to specify whether panel is using cphy.



- qcom,compression-mode:		Select compression mode for panel.

					"fbc" - frame buffer compression

drivers/clk/qcom/mdss/mdss-dsi-pll-10nm.c

+268 −51

File changed.

Preview size limit exceeded, changes collapsed.

drivers/clk/qcom/mdss/mdss-dsi-pll-7nm.c

+275 −57

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/msm/dsi-staging/dsi_clk.h

+6 −2
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -117,11 +117,13 @@ struct dsi_link_lp_clk_info { 
/**

 * struct link_clk_freq - Clock frequency information for Link clocks

 * @byte_clk_rate:   Frequency of DSI byte_clk in KHz.

 * @byte_intf_clk_rate:   Frequency of DSI byte_intf_clk in KHz.

 * @pixel_clk_rate:  Frequency of DSI pixel_clk in KHz.

 * @esc_clk_rate:    Frequency of DSI escape clock in KHz.

 */

struct link_clk_freq {

	u32 byte_clk_rate;

	u32 byte_intf_clk_rate;

	u32 pix_clk_rate;

	u32 esc_clk_rate;

};
@@ -306,10 +308,12 @@ int dsi_clk_set_pixel_clk_rate(void *client, u64 pixel_clk, u32 index); 
 * dsi_clk_set_byte_clk_rate() - set frequency for byte clock

 * @client:       DSI clock client pointer.

 * @byte_clk: Pixel clock rate in Hz.

 * @byte_intf_clk: Byte interface clock rate in Hz.

 * @index:      Index of the DSI controller.

 * return: error code in case of failure or 0 for success.

 */

int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index);

int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk,

				u64 byte_intf_clk, u32 index);



/**

 * dsi_clk_update_parent() - update parent clocks for specified clock

drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c

+9 −8
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -139,15 +139,16 @@ int dsi_clk_set_pixel_clk_rate(void *client, u64 pixel_clk, u32 index) 
 * dsi_clk_set_byte_clk_rate() - set frequency for byte clock

 * @client:	DSI clock client pointer.

 * @byte_clk:	Byte clock rate in Hz.

 * @byte_intf_clk: Byte interface clock rate in Hz.

 * @index:	Index of the DSI controller.

 * return: error code in case of failure or 0 for success.

 */

int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index)

int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk,

					u64 byte_intf_clk, u32 index)

{

	int rc = 0;

	struct dsi_clk_client_info *c = client;

	struct dsi_clk_mngr *mngr;

	u64 byte_intf_rate;



	mngr = c->mngr;

	rc = clk_set_rate(mngr->link_clks[index].hs_clks.byte_clk, byte_clk);
@@ -157,12 +158,14 @@ int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index) 
		mngr->link_clks[index].freq.byte_clk_rate = byte_clk;



	if (mngr->link_clks[index].hs_clks.byte_intf_clk) {

		byte_intf_rate = mngr->link_clks[index].freq.byte_clk_rate / 2;

		rc = clk_set_rate(mngr->link_clks[index].hs_clks.byte_intf_clk,

				  byte_intf_rate);

							byte_intf_clk);

		if (rc)

			pr_err("failed to set clk rate for byte intf clk=%d\n",

			       rc);

		else

			mngr->link_clks[index].freq.byte_intf_clk_rate

							= byte_intf_clk;

	}



	return rc;
@@ -371,12 +374,10 @@ static int dsi_link_hs_clk_set_rate(struct dsi_link_hs_clk_info *link_hs_clks, 


	/*

	 * If byte_intf_clk is present, set rate for that too.

	 * For DPHY: byte_intf_clk_rate = byte_clk_rate / 2

	 * todo: this needs to be revisited when support for CPHY is added

	 */

	if (link_hs_clks->byte_intf_clk) {

		rc = clk_set_rate(link_hs_clks->byte_intf_clk,

			(l_clks->freq.byte_clk_rate / 2));

				l_clks->freq.byte_intf_clk_rate);

		if (rc) {

			pr_err("set_rate failed for byte_intf_clk rc = %d\n",

				rc);