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Commit e991d514 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: enable SiRF GNSS Driver and hsuart1"

parents 3cae1640 d1e01625

arch/arm64/boot/dts/qcom/sa6155-adp-air.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -43,6 +43,13 @@ 
		};

	};



	ss5_pwr_ctrl0 {

		compatible = "gnss_sirf";

		pinctrl-0 = <&ss5_pwr_ctrl_rst_on>;

		ssVreset-gpio = <&tlmm 87 1>;

		ssVonoff-gpio = <&tlmm 18 1>;

	};



	hsi2s: qcom,hsi2s {

		compatible = "qcom,hsi2s";

		number-of-interfaces = <2>;
@@ -251,6 +258,10 @@ 
	status = "ok";

};



&qupv3_se4_2uart {

	status = "ok";

};



&qupv3_se7_4uart {

	status = "ok";

};

arch/arm64/boot/dts/qcom/sm6150-pinctrl.dtsi

+57 −0
Original line number Diff line number Diff line
@@ -260,6 +260,36 @@ 
			};

		};



		ss5_pwr_ctrl_pins: ss5_pwr_ctrl_pins {

			ss5_pwr_ctrl_rst_on: ss5_pwr_ctrl_rst_on {

				mux {

					pins = "gpio87", "gpio18";

					function = "gpio";

				};



				config {

					pins = "gpio87", "gpio18";

					drive-strength = <16>; /* 16 mA */

					bias-pull-up;

					output-high;

				};

			};



			ss5_pwr_ctrl_rst_off: ss5_pwr_ctrl_off {

				mux {

					pins = "gpio87", "gpio18";

					function = "gpio";

				};



				config {

					pins = "gpio87", "gpio18";

					drive-strength = <16>; /* 16 mA */

					bias-pull-up;

					output-high;

				};

			};

		};



		/* QUPv3_1 North instances */

		/* SE 4 pin mappings */

		qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
@@ -321,6 +351,33 @@ 
				};

			};

		};

		qupv3_se4_2uart_pins: qupv3_se4_2uart_pins {

			qupv3_se4_2uart_active: qupv3_se4_2uart_active {

				mux {

					pins = "gpio22", "gpio23";

					function = "qup10";

				};



				config {

					pins = "gpio22", "gpio23";

					drive-strength = <16>;

					bias-disable;

				};

			};



			qupv3_se4_2uart_sleep: qupv3_se4_2uart_sleep {

				mux {

					pins = "gpio22", "gpio23";

					function = "gpio";

				};



				config {

					pins = "gpio22", "gpio23";

					drive-strength = <16>;

					bias-disable;

				};

			};

		};



		/* SE 5 pin mappings */

		qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {

arch/arm64/boot/dts/qcom/sm6150-qupv3.dtsi

+17 −0
Original line number Diff line number Diff line
@@ -154,6 +154,23 @@ 
		};

	};



	/* GNSS UART Instance for CDP/MTP platform */

	qupv3_se4_2uart: qcom,qup_uart@0xa80000 {

		compatible = "qcom,msm-geni-serial-hs";

		reg = <0xa80000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se4_2uart_active>;

		pinctrl-1 = <&qupv3_se4_2uart_sleep>;

		interrupts = <GIC_SPI 353 0>;

		qcom,wrapper-core = <&qupv3_1>;

		status = "disabled";

	};



	/* I2C */

	qupv3_se4_i2c: i2c@a80000 {

		compatible = "qcom,i2c-geni";

arch/arm64/boot/dts/qcom/sm6150.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ 
		i2c1 = &qupv3_se1_i2c;

		i2c2 = &qupv3_se3_i2c;

		hsuart0 = &qupv3_se7_4uart;

		hsuart1 = &qupv3_se4_2uart;

		swr0 = &swr0;

		swr1 = &swr1;

		swr2 = &swr2;