Loading drivers/net/ethernet/stmicro/stmmac/common.h +2 −2 Original line number Diff line number Diff line Loading @@ -447,9 +447,9 @@ struct stmmac_dma_ops { void (*dma_mode)(void __iomem *ioaddr, int txmode, int rxmode, int rxfifosz); void (*dma_rx_mode)(void __iomem *ioaddr, int mode, u32 channel, int fifosz); int fifosz, u8 qmode); void (*dma_tx_mode)(void __iomem *ioaddr, int mode, u32 channel, int fifosz); int fifosz, u8 qmode); /* To track extra statistic (if supported) */ void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x, void __iomem *ioaddr); Loading drivers/net/ethernet/stmicro/stmmac/dwmac4.h +2 −0 Original line number Diff line number Diff line Loading @@ -229,6 +229,8 @@ enum power_event { #define MTL_CHAN_RX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x38) #define MTL_OP_MODE_RSF BIT(5) #define MTL_OP_MODE_TXQEN_MASK GENMASK(3, 2) #define MTL_OP_MODE_TXQEN_AV BIT(2) #define MTL_OP_MODE_TXQEN BIT(3) #define MTL_OP_MODE_TSF BIT(1) Loading drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +11 −5 Original line number Diff line number Diff line Loading @@ -191,7 +191,7 @@ static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 number_chan) } static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode, u32 channel, int fifosz) u32 channel, int fifosz, u8 qmode) { unsigned int rqs = fifosz / 256 - 1; u32 mtl_rx_op, mtl_rx_int; Loading @@ -218,8 +218,10 @@ static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode, mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK; mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT; /* enable flow control only if each channel gets 4 KiB or more FIFO */ if (fifosz >= 4096) { /* Enable flow control only if each channel gets 4 KiB or more FIFO and * only if channel is not an AVB channel. */ if (fifosz >= 4096 && qmode != MTL_QUEUE_AVB) { unsigned int rfd, rfa; mtl_rx_op |= MTL_OP_MODE_EHFC; Loading Loading @@ -271,7 +273,7 @@ static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode, } static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode, u32 channel, int fifosz) u32 channel, int fifosz, u8 qmode) { u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel)); unsigned int tqs = fifosz / 256 - 1; Loading Loading @@ -311,7 +313,11 @@ static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode, * reflect the available fifo size per queue (total fifo size / number * of enabled queues). */ mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK; if (qmode != MTL_QUEUE_AVB) mtl_tx_op |= MTL_OP_MODE_TXQEN; else mtl_tx_op |= MTL_OP_MODE_TXQEN_AV; mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK; mtl_tx_op |= tqs << MTL_OP_MODE_TQS_SHIFT; Loading drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +13 −5 Original line number Diff line number Diff line Loading @@ -1867,6 +1867,7 @@ static void stmmac_dma_operation_mode(struct stmmac_priv *priv) u32 rxmode = 0; u32 chan = 0; u32 mtl_rx_int; u8 qmode = 0; if (rxfifosz == 0) rxfifosz = priv->dma_cap.rx_fifo_size; Loading Loading @@ -1899,8 +1900,10 @@ static void stmmac_dma_operation_mode(struct stmmac_priv *priv) /* configure all channels */ if (priv->synopsys_id >= DWMAC_CORE_4_00) { for (chan = 0; chan < rx_channels_count; chan++) { qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; priv->hw->dma->dma_rx_mode(priv->ioaddr, rxmode, chan, rxfifosz); rxfifosz, qmode); if (priv->rx_queue[chan].skip_sw) { mtl_rx_int = readl_relaxed(priv->ioaddr + (0x00000d00 + 0x2c)); Loading @@ -1910,9 +1913,12 @@ static void stmmac_dma_operation_mode(struct stmmac_priv *priv) } } for (chan = 0; chan < tx_channels_count; chan++) for (chan = 0; chan < tx_channels_count; chan++) { qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; priv->hw->dma->dma_tx_mode(priv->ioaddr, txmode, chan, txfifosz); txfifosz, qmode); } } else { priv->hw->dma->dma_mode(priv->ioaddr, txmode, rxmode, rxfifosz); Loading Loading @@ -2095,6 +2101,8 @@ static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, u32 rxmode, u32 chan) { u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; u32 rx_channels_count = priv->plat->rx_queues_to_use; u32 tx_channels_count = priv->plat->tx_queues_to_use; int rxfifosz = priv->plat->rx_fifo_size; Loading @@ -2111,9 +2119,9 @@ static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, if (priv->synopsys_id >= DWMAC_CORE_4_00) { priv->hw->dma->dma_rx_mode(priv->ioaddr, rxmode, chan, rxfifosz); rxfifosz, rxqmode); priv->hw->dma->dma_tx_mode(priv->ioaddr, txmode, chan, txfifosz); txfifosz, txqmode); } else { priv->hw->dma->dma_mode(priv->ioaddr, txmode, rxmode, rxfifosz); Loading Loading
drivers/net/ethernet/stmicro/stmmac/common.h +2 −2 Original line number Diff line number Diff line Loading @@ -447,9 +447,9 @@ struct stmmac_dma_ops { void (*dma_mode)(void __iomem *ioaddr, int txmode, int rxmode, int rxfifosz); void (*dma_rx_mode)(void __iomem *ioaddr, int mode, u32 channel, int fifosz); int fifosz, u8 qmode); void (*dma_tx_mode)(void __iomem *ioaddr, int mode, u32 channel, int fifosz); int fifosz, u8 qmode); /* To track extra statistic (if supported) */ void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x, void __iomem *ioaddr); Loading
drivers/net/ethernet/stmicro/stmmac/dwmac4.h +2 −0 Original line number Diff line number Diff line Loading @@ -229,6 +229,8 @@ enum power_event { #define MTL_CHAN_RX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x38) #define MTL_OP_MODE_RSF BIT(5) #define MTL_OP_MODE_TXQEN_MASK GENMASK(3, 2) #define MTL_OP_MODE_TXQEN_AV BIT(2) #define MTL_OP_MODE_TXQEN BIT(3) #define MTL_OP_MODE_TSF BIT(1) Loading
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +11 −5 Original line number Diff line number Diff line Loading @@ -191,7 +191,7 @@ static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 number_chan) } static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode, u32 channel, int fifosz) u32 channel, int fifosz, u8 qmode) { unsigned int rqs = fifosz / 256 - 1; u32 mtl_rx_op, mtl_rx_int; Loading @@ -218,8 +218,10 @@ static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode, mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK; mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT; /* enable flow control only if each channel gets 4 KiB or more FIFO */ if (fifosz >= 4096) { /* Enable flow control only if each channel gets 4 KiB or more FIFO and * only if channel is not an AVB channel. */ if (fifosz >= 4096 && qmode != MTL_QUEUE_AVB) { unsigned int rfd, rfa; mtl_rx_op |= MTL_OP_MODE_EHFC; Loading Loading @@ -271,7 +273,7 @@ static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode, } static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode, u32 channel, int fifosz) u32 channel, int fifosz, u8 qmode) { u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel)); unsigned int tqs = fifosz / 256 - 1; Loading Loading @@ -311,7 +313,11 @@ static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode, * reflect the available fifo size per queue (total fifo size / number * of enabled queues). */ mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK; if (qmode != MTL_QUEUE_AVB) mtl_tx_op |= MTL_OP_MODE_TXQEN; else mtl_tx_op |= MTL_OP_MODE_TXQEN_AV; mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK; mtl_tx_op |= tqs << MTL_OP_MODE_TQS_SHIFT; Loading
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +13 −5 Original line number Diff line number Diff line Loading @@ -1867,6 +1867,7 @@ static void stmmac_dma_operation_mode(struct stmmac_priv *priv) u32 rxmode = 0; u32 chan = 0; u32 mtl_rx_int; u8 qmode = 0; if (rxfifosz == 0) rxfifosz = priv->dma_cap.rx_fifo_size; Loading Loading @@ -1899,8 +1900,10 @@ static void stmmac_dma_operation_mode(struct stmmac_priv *priv) /* configure all channels */ if (priv->synopsys_id >= DWMAC_CORE_4_00) { for (chan = 0; chan < rx_channels_count; chan++) { qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; priv->hw->dma->dma_rx_mode(priv->ioaddr, rxmode, chan, rxfifosz); rxfifosz, qmode); if (priv->rx_queue[chan].skip_sw) { mtl_rx_int = readl_relaxed(priv->ioaddr + (0x00000d00 + 0x2c)); Loading @@ -1910,9 +1913,12 @@ static void stmmac_dma_operation_mode(struct stmmac_priv *priv) } } for (chan = 0; chan < tx_channels_count; chan++) for (chan = 0; chan < tx_channels_count; chan++) { qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; priv->hw->dma->dma_tx_mode(priv->ioaddr, txmode, chan, txfifosz); txfifosz, qmode); } } else { priv->hw->dma->dma_mode(priv->ioaddr, txmode, rxmode, rxfifosz); Loading Loading @@ -2095,6 +2101,8 @@ static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, u32 rxmode, u32 chan) { u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; u32 rx_channels_count = priv->plat->rx_queues_to_use; u32 tx_channels_count = priv->plat->tx_queues_to_use; int rxfifosz = priv->plat->rx_fifo_size; Loading @@ -2111,9 +2119,9 @@ static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, if (priv->synopsys_id >= DWMAC_CORE_4_00) { priv->hw->dma->dma_rx_mode(priv->ioaddr, rxmode, chan, rxfifosz); rxfifosz, rxqmode); priv->hw->dma->dma_tx_mode(priv->ioaddr, txmode, chan, txfifosz); txfifosz, txqmode); } else { priv->hw->dma->dma_mode(priv->ioaddr, txmode, rxmode, rxfifosz); Loading