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Commit e93096a4 authored by Govinda Rajulu Chenna's avatar Govinda Rajulu Chenna
Browse files

drm/msm/dp: add debugfs node to set/get max pclk 



Add debug fs node, max_pclk_khz, to configure the maximum PCLK
supported. The maximum PCLK value limits the maximum resolution
and fps supported for the connected external display.

Example: To set 650MHz PCLK: echo 650000 > /d/drm_dp/max_pclk_khz

CRs-Fixed: 2252931
Change-Id: If17989616e31ed44256affee120917b92ef892e9
Signed-off-by: default avatarGovinda Rajulu Chenna <gchenna@codeaurora.org>
parent da658422

drivers/gpu/drm/msm/dp/dp_debug.c

+80 −0
Original line number Original line Diff line number Diff line
@@ -399,6 +399,72 @@ static ssize_t dp_debug_mst_mode_write(struct file *file, 
	return len;

	return len;

}

}





static ssize_t dp_debug_max_pclk_khz_write(struct file *file,

		const char __user *user_buff, size_t count, loff_t *ppos)

{

	struct dp_debug_private *debug = file->private_data;

	char buf[SZ_8];

	size_t len = 0;

	u32 max_pclk = 0;



	if (!debug)

		return -ENODEV;



	if (*ppos)

		return 0;



	len = min_t(size_t, count, SZ_8 - 1);

	if (copy_from_user(buf, user_buff, len))

		return 0;



	buf[len] = '\0';



	if (kstrtoint(buf, 10, &max_pclk) != 0)

		return 0;



	if (max_pclk > debug->parser->max_pclk_khz)

		pr_err("requested: %d, max_pclk_khz:%d\n", max_pclk,

				debug->parser->max_pclk_khz);

	else

		debug->dp_debug.max_pclk_khz = max_pclk;



	pr_debug("max_pclk_khz: %d\n", max_pclk);



	return len;

}



static ssize_t dp_debug_max_pclk_khz_read(struct file *file,

	char __user *user_buff, size_t count, loff_t *ppos)

{

	struct dp_debug_private *debug = file->private_data;

	char *buf;

	u32 len = 0;



	if (!debug)

		return -ENODEV;



	if (*ppos)

		return 0;



	buf = kzalloc(SZ_4K, GFP_KERNEL);

	if (!buf)

		return -ENOMEM;



	len += snprintf(buf + len, (SZ_4K - len),

			"max_pclk_khz = %d, org: %d\n",

			debug->dp_debug.max_pclk_khz,

			debug->parser->max_pclk_khz);



	if (copy_to_user(user_buff, buf, len)) {

		kfree(buf);

		return -EFAULT;

	}



	*ppos += len;

	kfree(buf);

	return len;

}



static ssize_t dp_debug_mst_sideband_mode_write(struct file *file,

static ssize_t dp_debug_mst_sideband_mode_write(struct file *file,

		const char __user *user_buff, size_t count, loff_t *ppos)

		const char __user *user_buff, size_t count, loff_t *ppos)

{

{
@@ -1154,6 +1220,12 @@ static const struct file_operations mst_sideband_mode_fops = { 
	.write = dp_debug_mst_sideband_mode_write,

	.write = dp_debug_mst_sideband_mode_write,

};

};





static const struct file_operations max_pclk_khz_fops = {

	.open = simple_open,

	.write = dp_debug_max_pclk_khz_write,

	.read = dp_debug_max_pclk_khz_read,

};



static int dp_debug_init(struct dp_debug *dp_debug)

static int dp_debug_init(struct dp_debug *dp_debug)

{

{

	int rc = 0;

	int rc = 0;
@@ -1309,6 +1381,14 @@ static int dp_debug_init(struct dp_debug *dp_debug) 
		       DEBUG_NAME, rc);

		       DEBUG_NAME, rc);

	}

	}





	file = debugfs_create_file("max_pclk_khz", 0644, dir,

			debug, &max_pclk_khz_fops);

	if (IS_ERR_OR_NULL(file)) {

		rc = PTR_ERR(file);

		pr_err("[%s] debugfs max_pclk_khz failed, rc=%d\n",

		       DEBUG_NAME, rc);

	}



	return 0;

	return 0;





error_remove_dir:

error_remove_dir:

drivers/gpu/drm/msm/dp/dp_debug.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -27,6 +27,7 @@ 
 * @hdisplay: used to filter out hdisplay value

 * @hdisplay: used to filter out hdisplay value

 * @vrefresh: used to filter out vrefresh value

 * @vrefresh: used to filter out vrefresh value

 * @tpg_state: specifies whether tpg feature is enabled

 * @tpg_state: specifies whether tpg feature is enabled

 * @max_pclk_khz: max pclk supported

 */

 */

struct dp_debug {

struct dp_debug {

	bool debug_en;

	bool debug_en;
@@ -37,6 +38,7 @@ struct dp_debug { 
	int hdisplay;

	int hdisplay;

	int vrefresh;

	int vrefresh;

	bool tpg_state;

	bool tpg_state;

	u32 max_pclk_khz;





	u8 *(*get_edid)(struct dp_debug *dp_debug);

	u8 *(*get_edid)(struct dp_debug *dp_debug);

};

};

drivers/gpu/drm/msm/dp/dp_display.c

+6 −1
Original line number Original line Diff line number Diff line
@@ -564,8 +564,13 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp) 
	dp->link->process_request(dp->link);

	dp->link->process_request(dp->link);

	dp->panel->handle_sink_request(dp->panel);

	dp->panel->handle_sink_request(dp->panel);





	if (dp->debug->max_pclk_khz)

		dp->dp_display.max_pclk_khz = dp->debug->max_pclk_khz;

	else

		dp->dp_display.max_pclk_khz = dp->parser->max_pclk_khz;

		dp->dp_display.max_pclk_khz = dp->parser->max_pclk_khz;





	pr_debug("dp max_pclk_khz = %d\n", dp->dp_display.max_pclk_khz);



	dp_display_process_mst_hpd_high(dp);

	dp_display_process_mst_hpd_high(dp);

notify:

notify:

	dp_display_send_hpd_notification(dp, true);

	dp_display_send_hpd_notification(dp, true);