Loading arch/arm64/boot/dts/qcom/sm6150-camera.dtsi +6 −0 Original line number Original line Diff line number Diff line Loading @@ -894,6 +894,9 @@ cam_ipe0: qcom,ipe0 { cam_ipe0: qcom,ipe0 { cell-index = <0>; cell-index = <0>; compatible = "qcom,cam-ipe"; compatible = "qcom,cam-ipe"; reg = <0xac87000 0x3000>; reg-names = "ipe0_top"; reg-cam-base = <0x87000>; regulator-names = "ipe0-vdd"; regulator-names = "ipe0-vdd"; ipe0-vdd-supply = <&ipe_0_gdsc>; ipe0-vdd-supply = <&ipe_0_gdsc>; clock-names = "ipe_0_ahb_clk", clock-names = "ipe_0_ahb_clk", Loading Loading @@ -922,6 +925,9 @@ cam_bps: qcom,bps { cam_bps: qcom,bps { cell-index = <0>; cell-index = <0>; compatible = "qcom,cam-bps"; compatible = "qcom,cam-bps"; reg = <0xac6f000 0x3000>; reg-names = "bps_top"; reg-cam-base = <0x6f000>; regulator-names = "bps-vdd"; regulator-names = "bps-vdd"; bps-vdd-supply = <&bps_gdsc>; bps-vdd-supply = <&bps_gdsc>; clock-names = "bps_ahb_clk", clock-names = "bps_ahb_clk", Loading arch/arm64/boot/dts/qcom/sm8150-camera.dtsi +24 −14 Original line number Original line Diff line number Diff line Loading @@ -733,10 +733,11 @@ <&clock_camcc CAM_CC_IFE_0_CLK>, <&clock_camcc CAM_CC_IFE_0_CLK>, <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; clock-rates = clock-rates = <400000000 0 0 0 400000000 0 0>, <400000000 0 0 0 558000000 0 0>, <400000000 0 0 0 558000000 0 0>, <480000000 0 0 0 637000000 0 0>, <480000000 0 0 0 637000000 0 0>, <600000000 0 0 0 760000000 0 0>; <600000000 0 0 0 760000000 0 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; src-clock-name = "ife_csid_clk_src"; src-clock-name = "ife_csid_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; status = "ok"; status = "ok"; Loading @@ -745,9 +746,10 @@ cam_vfe0: qcom,vfe0@acaf000 { cam_vfe0: qcom,vfe0@acaf000 { cell-index = <0>; cell-index = <0>; compatible = "qcom,vfe175"; compatible = "qcom,vfe175"; reg-names = "ife"; reg-names = "ife", "cam_camnoc"; reg = <0xacaf000 0x4000>; reg = <0xacaf000 0x4000>, reg-cam-base = <0xaf000>; <0xac42000 0x5000>; reg-cam-base = <0xaf000 0x42000>; interrupt-names = "ife"; interrupt-names = "ife"; interrupts = <0 465 0>; interrupts = <0 465 0>; regulator-names = "camss", "ife0"; regulator-names = "camss", "ife0"; Loading @@ -762,10 +764,11 @@ <&clock_camcc CAM_CC_IFE_0_CLK>, <&clock_camcc CAM_CC_IFE_0_CLK>, <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; clock-rates = clock-rates = <400000000 0 0>, <558000000 0 0>, <558000000 0 0>, <637000000 0 0>, <637000000 0 0>, <760000000 0 0>; <760000000 0 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; src-clock-name = "ife_clk_src"; src-clock-name = "ife_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; clock-names-option = "ife_dsp_clk"; clock-names-option = "ife_dsp_clk"; Loading Loading @@ -802,10 +805,11 @@ <&clock_camcc CAM_CC_IFE_1_CLK>, <&clock_camcc CAM_CC_IFE_1_CLK>, <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; clock-rates = clock-rates = <400000000 0 0 0 400000000 0 0>, <400000000 0 0 0 558000000 0 0>, <400000000 0 0 0 558000000 0 0>, <480000000 0 0 0 637000000 0 0>, <480000000 0 0 0 637000000 0 0>, <600000000 0 0 0 760000000 0 0>; <600000000 0 0 0 760000000 0 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; src-clock-name = "ife_csid_clk_src"; src-clock-name = "ife_csid_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; status = "ok"; status = "ok"; Loading @@ -814,9 +818,10 @@ cam_vfe1: qcom,vfe1@acb6000 { cam_vfe1: qcom,vfe1@acb6000 { cell-index = <1>; cell-index = <1>; compatible = "qcom,vfe175"; compatible = "qcom,vfe175"; reg-names = "ife"; reg-names = "ife", "cam_camnoc"; reg = <0xacb6000 0x4000>; reg = <0xacb6000 0x4000>, reg-cam-base = <0xb6000>; <0xac42000 0x5000>; reg-cam-base = <0xb6000 0x42000>; interrupt-names = "ife"; interrupt-names = "ife"; interrupts = <0 467 0>; interrupts = <0 467 0>; regulator-names = "camss", "ife1"; regulator-names = "camss", "ife1"; Loading @@ -831,10 +836,11 @@ <&clock_camcc CAM_CC_IFE_1_CLK>, <&clock_camcc CAM_CC_IFE_1_CLK>, <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; clock-rates = clock-rates = <400000000 0 0>, <558000000 0 0>, <558000000 0 0>, <637000000 0 0>, <637000000 0 0>, <760000000 0 0>; <760000000 0 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; src-clock-name = "ife_clk_src"; src-clock-name = "ife_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; clock-names-option = "ife_dsp_clk"; clock-names-option = "ife_dsp_clk"; Loading Loading @@ -868,10 +874,11 @@ <&clock_camcc CAM_CC_IFE_LITE_0_CLK_SRC>, <&clock_camcc CAM_CC_IFE_LITE_0_CLK_SRC>, <&clock_camcc CAM_CC_IFE_LITE_0_CLK>; <&clock_camcc CAM_CC_IFE_LITE_0_CLK>; clock-rates = clock-rates = <400000000 0 0 0 320000000 0>, <400000000 0 0 0 400000000 0>, <400000000 0 0 0 400000000 0>, <480000000 0 0 0 480000000 0>, <480000000 0 0 0 480000000 0>, <600000000 0 0 0 600000000 0>; <600000000 0 0 0 600000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; src-clock-name = "ife_csid_clk_src"; src-clock-name = "ife_csid_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; status = "ok"; status = "ok"; Loading @@ -894,10 +901,11 @@ <&clock_camcc CAM_CC_IFE_LITE_0_CLK_SRC>, <&clock_camcc CAM_CC_IFE_LITE_0_CLK_SRC>, <&clock_camcc CAM_CC_IFE_LITE_0_CLK>; <&clock_camcc CAM_CC_IFE_LITE_0_CLK>; clock-rates = clock-rates = <320000000 0>, <400000000 0>, <400000000 0>, <480000000 0>, <480000000 0>, <600000000 0>; <600000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; src-clock-name = "ife_clk_src"; src-clock-name = "ife_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; status = "ok"; status = "ok"; Loading Loading @@ -928,10 +936,11 @@ <&clock_camcc CAM_CC_IFE_LITE_1_CLK_SRC>, <&clock_camcc CAM_CC_IFE_LITE_1_CLK_SRC>, <&clock_camcc CAM_CC_IFE_LITE_1_CLK>; <&clock_camcc CAM_CC_IFE_LITE_1_CLK>; clock-rates = clock-rates = <400000000 0 0 0 320000000 0>, <400000000 0 0 0 400000000 0>, <400000000 0 0 0 400000000 0>, <480000000 0 0 0 480000000 0>, <480000000 0 0 0 480000000 0>, <600000000 0 0 0 600000000 0>; <600000000 0 0 0 600000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; src-clock-name = "ife_csid_clk_src"; src-clock-name = "ife_csid_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; status = "ok"; status = "ok"; Loading @@ -954,10 +963,11 @@ <&clock_camcc CAM_CC_IFE_LITE_1_CLK_SRC>, <&clock_camcc CAM_CC_IFE_LITE_1_CLK_SRC>, <&clock_camcc CAM_CC_IFE_LITE_1_CLK>; <&clock_camcc CAM_CC_IFE_LITE_1_CLK>; clock-rates = clock-rates = <320000000 0>, <400000000 0>, <400000000 0>, <480000000 0>, <480000000 0>, <600000000 0>; <600000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; src-clock-name = "ife_clk_src"; src-clock-name = "ife_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; status = "ok"; status = "ok"; Loading arch/arm64/boot/dts/qcom/sm8150-v2-camera.dtsi +20 −10 Original line number Original line Diff line number Diff line Loading @@ -15,9 +15,10 @@ cam_vfe0: qcom,vfe0@acaf000 { cam_vfe0: qcom,vfe0@acaf000 { cell-index = <0>; cell-index = <0>; compatible = "qcom,vfe175"; compatible = "qcom,vfe175"; reg-names = "ife"; reg-names = "ife", "cam_camnoc"; reg = <0xacaf000 0x4000>; reg = <0xacaf000 0x4000>, reg-cam-base = <0xaf000>; <0xac42000 0x5000>; reg-cam-base = <0xaf000 0x42000>; interrupt-names = "ife"; interrupt-names = "ife"; interrupts = <0 465 0>; interrupts = <0 465 0>; regulator-names = "camss", "ife0"; regulator-names = "camss", "ife0"; Loading @@ -32,11 +33,13 @@ <&clock_camcc CAM_CC_IFE_0_CLK>, <&clock_camcc CAM_CC_IFE_0_CLK>, <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; clock-rates = clock-rates = <400000000 0 0>, <558000000 0 0>, <558000000 0 0>, <637000000 0 0>, <637000000 0 0>, <847000000 0 0>, <847000000 0 0>, <950000000 0 0>; <950000000 0 0>; clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_clk_src"; src-clock-name = "ife_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; clock-names-option = "ife_dsp_clk"; clock-names-option = "ife_dsp_clk"; Loading Loading @@ -73,11 +76,13 @@ <&clock_camcc CAM_CC_IFE_0_CLK>, <&clock_camcc CAM_CC_IFE_0_CLK>, <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; clock-rates = clock-rates = <400000000 0 0 0 400000000 0 0>, <400000000 0 0 0 558000000 0 0>, <400000000 0 0 0 558000000 0 0>, <480000000 0 0 0 637000000 0 0>, <480000000 0 0 0 637000000 0 0>, <600000000 0 0 0 847000000 0 0>, <600000000 0 0 0 847000000 0 0>, <600000000 0 0 0 950000000 0 0>; <600000000 0 0 0 950000000 0 0>; clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_csid_clk_src"; src-clock-name = "ife_csid_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; status = "ok"; status = "ok"; Loading @@ -86,9 +91,10 @@ cam_vfe1: qcom,vfe1@acb6000 { cam_vfe1: qcom,vfe1@acb6000 { cell-index = <1>; cell-index = <1>; compatible = "qcom,vfe175"; compatible = "qcom,vfe175"; reg-names = "ife"; reg-names = "ife", "cam_camnoc"; reg = <0xacb6000 0x4000>; reg = <0xacb6000 0x4000>, reg-cam-base = <0xb6000>; <0xac42000 0x5000>; reg-cam-base = <0xb6000 0x42000>; interrupt-names = "ife"; interrupt-names = "ife"; interrupts = <0 467 0>; interrupts = <0 467 0>; regulator-names = "camss", "ife1"; regulator-names = "camss", "ife1"; Loading @@ -103,11 +109,13 @@ <&clock_camcc CAM_CC_IFE_1_CLK>, <&clock_camcc CAM_CC_IFE_1_CLK>, <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; clock-rates = clock-rates = <400000000 0 0>, <558000000 0 0>, <558000000 0 0>, <637000000 0 0>, <637000000 0 0>, <847000000 0 0>, <847000000 0 0>, <950000000 0 0>; <950000000 0 0>; clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_clk_src"; src-clock-name = "ife_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; clock-names-option = "ife_dsp_clk"; clock-names-option = "ife_dsp_clk"; Loading Loading @@ -144,11 +152,13 @@ <&clock_camcc CAM_CC_IFE_1_CLK>, <&clock_camcc CAM_CC_IFE_1_CLK>, <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; clock-rates = clock-rates = <400000000 0 0 0 400000000 0 0>, <400000000 0 0 0 558000000 0 0>, <400000000 0 0 0 558000000 0 0>, <480000000 0 0 0 637000000 0 0>, <480000000 0 0 0 637000000 0 0>, <600000000 0 0 0 847000000 0 0>, <600000000 0 0 0 847000000 0 0>, <600000000 0 0 0 950000000 0 0>; <600000000 0 0 0 950000000 0 0>; clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_csid_clk_src"; src-clock-name = "ife_csid_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; status = "ok"; status = "ok"; Loading drivers/media/platform/msm/camera/cam_core/cam_context.c +1 −0 Original line number Original line Diff line number Diff line Loading @@ -448,6 +448,7 @@ int cam_context_handle_start_dev(struct cam_context *ctx, } } mutex_lock(&ctx->ctx_mutex); mutex_lock(&ctx->ctx_mutex); ctx->last_flush_req = 0; if (ctx->state_machine[ctx->state].ioctl_ops.start_dev) if (ctx->state_machine[ctx->state].ioctl_ops.start_dev) rc = ctx->state_machine[ctx->state].ioctl_ops.start_dev( rc = ctx->state_machine[ctx->state].ioctl_ops.start_dev( ctx, cmd); ctx, cmd); Loading drivers/media/platform/msm/camera/cam_core/cam_context.h +2 −0 Original line number Original line Diff line number Diff line Loading @@ -180,6 +180,7 @@ struct cam_ctx_ops { * @refcount: Context object refcount * @refcount: Context object refcount * @node: The main node to which this context belongs * @node: The main node to which this context belongs * @sync_mutex: mutex to sync with sync cb thread * @sync_mutex: mutex to sync with sync cb thread * @last_flush_req: Last request to flush * * */ */ struct cam_context { struct cam_context { Loading Loading @@ -215,6 +216,7 @@ struct cam_context { struct kref refcount; struct kref refcount; void *node; void *node; struct mutex sync_mutex; struct mutex sync_mutex; uint32_t last_flush_req; }; }; /** /** Loading Loading
arch/arm64/boot/dts/qcom/sm6150-camera.dtsi +6 −0 Original line number Original line Diff line number Diff line Loading @@ -894,6 +894,9 @@ cam_ipe0: qcom,ipe0 { cam_ipe0: qcom,ipe0 { cell-index = <0>; cell-index = <0>; compatible = "qcom,cam-ipe"; compatible = "qcom,cam-ipe"; reg = <0xac87000 0x3000>; reg-names = "ipe0_top"; reg-cam-base = <0x87000>; regulator-names = "ipe0-vdd"; regulator-names = "ipe0-vdd"; ipe0-vdd-supply = <&ipe_0_gdsc>; ipe0-vdd-supply = <&ipe_0_gdsc>; clock-names = "ipe_0_ahb_clk", clock-names = "ipe_0_ahb_clk", Loading Loading @@ -922,6 +925,9 @@ cam_bps: qcom,bps { cam_bps: qcom,bps { cell-index = <0>; cell-index = <0>; compatible = "qcom,cam-bps"; compatible = "qcom,cam-bps"; reg = <0xac6f000 0x3000>; reg-names = "bps_top"; reg-cam-base = <0x6f000>; regulator-names = "bps-vdd"; regulator-names = "bps-vdd"; bps-vdd-supply = <&bps_gdsc>; bps-vdd-supply = <&bps_gdsc>; clock-names = "bps_ahb_clk", clock-names = "bps_ahb_clk", Loading
arch/arm64/boot/dts/qcom/sm8150-camera.dtsi +24 −14 Original line number Original line Diff line number Diff line Loading @@ -733,10 +733,11 @@ <&clock_camcc CAM_CC_IFE_0_CLK>, <&clock_camcc CAM_CC_IFE_0_CLK>, <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; clock-rates = clock-rates = <400000000 0 0 0 400000000 0 0>, <400000000 0 0 0 558000000 0 0>, <400000000 0 0 0 558000000 0 0>, <480000000 0 0 0 637000000 0 0>, <480000000 0 0 0 637000000 0 0>, <600000000 0 0 0 760000000 0 0>; <600000000 0 0 0 760000000 0 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; src-clock-name = "ife_csid_clk_src"; src-clock-name = "ife_csid_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; status = "ok"; status = "ok"; Loading @@ -745,9 +746,10 @@ cam_vfe0: qcom,vfe0@acaf000 { cam_vfe0: qcom,vfe0@acaf000 { cell-index = <0>; cell-index = <0>; compatible = "qcom,vfe175"; compatible = "qcom,vfe175"; reg-names = "ife"; reg-names = "ife", "cam_camnoc"; reg = <0xacaf000 0x4000>; reg = <0xacaf000 0x4000>, reg-cam-base = <0xaf000>; <0xac42000 0x5000>; reg-cam-base = <0xaf000 0x42000>; interrupt-names = "ife"; interrupt-names = "ife"; interrupts = <0 465 0>; interrupts = <0 465 0>; regulator-names = "camss", "ife0"; regulator-names = "camss", "ife0"; Loading @@ -762,10 +764,11 @@ <&clock_camcc CAM_CC_IFE_0_CLK>, <&clock_camcc CAM_CC_IFE_0_CLK>, <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; clock-rates = clock-rates = <400000000 0 0>, <558000000 0 0>, <558000000 0 0>, <637000000 0 0>, <637000000 0 0>, <760000000 0 0>; <760000000 0 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; src-clock-name = "ife_clk_src"; src-clock-name = "ife_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; clock-names-option = "ife_dsp_clk"; clock-names-option = "ife_dsp_clk"; Loading Loading @@ -802,10 +805,11 @@ <&clock_camcc CAM_CC_IFE_1_CLK>, <&clock_camcc CAM_CC_IFE_1_CLK>, <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; clock-rates = clock-rates = <400000000 0 0 0 400000000 0 0>, <400000000 0 0 0 558000000 0 0>, <400000000 0 0 0 558000000 0 0>, <480000000 0 0 0 637000000 0 0>, <480000000 0 0 0 637000000 0 0>, <600000000 0 0 0 760000000 0 0>; <600000000 0 0 0 760000000 0 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; src-clock-name = "ife_csid_clk_src"; src-clock-name = "ife_csid_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; status = "ok"; status = "ok"; Loading @@ -814,9 +818,10 @@ cam_vfe1: qcom,vfe1@acb6000 { cam_vfe1: qcom,vfe1@acb6000 { cell-index = <1>; cell-index = <1>; compatible = "qcom,vfe175"; compatible = "qcom,vfe175"; reg-names = "ife"; reg-names = "ife", "cam_camnoc"; reg = <0xacb6000 0x4000>; reg = <0xacb6000 0x4000>, reg-cam-base = <0xb6000>; <0xac42000 0x5000>; reg-cam-base = <0xb6000 0x42000>; interrupt-names = "ife"; interrupt-names = "ife"; interrupts = <0 467 0>; interrupts = <0 467 0>; regulator-names = "camss", "ife1"; regulator-names = "camss", "ife1"; Loading @@ -831,10 +836,11 @@ <&clock_camcc CAM_CC_IFE_1_CLK>, <&clock_camcc CAM_CC_IFE_1_CLK>, <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; clock-rates = clock-rates = <400000000 0 0>, <558000000 0 0>, <558000000 0 0>, <637000000 0 0>, <637000000 0 0>, <760000000 0 0>; <760000000 0 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; src-clock-name = "ife_clk_src"; src-clock-name = "ife_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; clock-names-option = "ife_dsp_clk"; clock-names-option = "ife_dsp_clk"; Loading Loading @@ -868,10 +874,11 @@ <&clock_camcc CAM_CC_IFE_LITE_0_CLK_SRC>, <&clock_camcc CAM_CC_IFE_LITE_0_CLK_SRC>, <&clock_camcc CAM_CC_IFE_LITE_0_CLK>; <&clock_camcc CAM_CC_IFE_LITE_0_CLK>; clock-rates = clock-rates = <400000000 0 0 0 320000000 0>, <400000000 0 0 0 400000000 0>, <400000000 0 0 0 400000000 0>, <480000000 0 0 0 480000000 0>, <480000000 0 0 0 480000000 0>, <600000000 0 0 0 600000000 0>; <600000000 0 0 0 600000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; src-clock-name = "ife_csid_clk_src"; src-clock-name = "ife_csid_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; status = "ok"; status = "ok"; Loading @@ -894,10 +901,11 @@ <&clock_camcc CAM_CC_IFE_LITE_0_CLK_SRC>, <&clock_camcc CAM_CC_IFE_LITE_0_CLK_SRC>, <&clock_camcc CAM_CC_IFE_LITE_0_CLK>; <&clock_camcc CAM_CC_IFE_LITE_0_CLK>; clock-rates = clock-rates = <320000000 0>, <400000000 0>, <400000000 0>, <480000000 0>, <480000000 0>, <600000000 0>; <600000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; src-clock-name = "ife_clk_src"; src-clock-name = "ife_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; status = "ok"; status = "ok"; Loading Loading @@ -928,10 +936,11 @@ <&clock_camcc CAM_CC_IFE_LITE_1_CLK_SRC>, <&clock_camcc CAM_CC_IFE_LITE_1_CLK_SRC>, <&clock_camcc CAM_CC_IFE_LITE_1_CLK>; <&clock_camcc CAM_CC_IFE_LITE_1_CLK>; clock-rates = clock-rates = <400000000 0 0 0 320000000 0>, <400000000 0 0 0 400000000 0>, <400000000 0 0 0 400000000 0>, <480000000 0 0 0 480000000 0>, <480000000 0 0 0 480000000 0>, <600000000 0 0 0 600000000 0>; <600000000 0 0 0 600000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; src-clock-name = "ife_csid_clk_src"; src-clock-name = "ife_csid_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; status = "ok"; status = "ok"; Loading @@ -954,10 +963,11 @@ <&clock_camcc CAM_CC_IFE_LITE_1_CLK_SRC>, <&clock_camcc CAM_CC_IFE_LITE_1_CLK_SRC>, <&clock_camcc CAM_CC_IFE_LITE_1_CLK>; <&clock_camcc CAM_CC_IFE_LITE_1_CLK>; clock-rates = clock-rates = <320000000 0>, <400000000 0>, <400000000 0>, <480000000 0>, <480000000 0>, <600000000 0>; <600000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; src-clock-name = "ife_clk_src"; src-clock-name = "ife_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; status = "ok"; status = "ok"; Loading
arch/arm64/boot/dts/qcom/sm8150-v2-camera.dtsi +20 −10 Original line number Original line Diff line number Diff line Loading @@ -15,9 +15,10 @@ cam_vfe0: qcom,vfe0@acaf000 { cam_vfe0: qcom,vfe0@acaf000 { cell-index = <0>; cell-index = <0>; compatible = "qcom,vfe175"; compatible = "qcom,vfe175"; reg-names = "ife"; reg-names = "ife", "cam_camnoc"; reg = <0xacaf000 0x4000>; reg = <0xacaf000 0x4000>, reg-cam-base = <0xaf000>; <0xac42000 0x5000>; reg-cam-base = <0xaf000 0x42000>; interrupt-names = "ife"; interrupt-names = "ife"; interrupts = <0 465 0>; interrupts = <0 465 0>; regulator-names = "camss", "ife0"; regulator-names = "camss", "ife0"; Loading @@ -32,11 +33,13 @@ <&clock_camcc CAM_CC_IFE_0_CLK>, <&clock_camcc CAM_CC_IFE_0_CLK>, <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; clock-rates = clock-rates = <400000000 0 0>, <558000000 0 0>, <558000000 0 0>, <637000000 0 0>, <637000000 0 0>, <847000000 0 0>, <847000000 0 0>, <950000000 0 0>; <950000000 0 0>; clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_clk_src"; src-clock-name = "ife_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; clock-names-option = "ife_dsp_clk"; clock-names-option = "ife_dsp_clk"; Loading Loading @@ -73,11 +76,13 @@ <&clock_camcc CAM_CC_IFE_0_CLK>, <&clock_camcc CAM_CC_IFE_0_CLK>, <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; clock-rates = clock-rates = <400000000 0 0 0 400000000 0 0>, <400000000 0 0 0 558000000 0 0>, <400000000 0 0 0 558000000 0 0>, <480000000 0 0 0 637000000 0 0>, <480000000 0 0 0 637000000 0 0>, <600000000 0 0 0 847000000 0 0>, <600000000 0 0 0 847000000 0 0>, <600000000 0 0 0 950000000 0 0>; <600000000 0 0 0 950000000 0 0>; clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_csid_clk_src"; src-clock-name = "ife_csid_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; status = "ok"; status = "ok"; Loading @@ -86,9 +91,10 @@ cam_vfe1: qcom,vfe1@acb6000 { cam_vfe1: qcom,vfe1@acb6000 { cell-index = <1>; cell-index = <1>; compatible = "qcom,vfe175"; compatible = "qcom,vfe175"; reg-names = "ife"; reg-names = "ife", "cam_camnoc"; reg = <0xacb6000 0x4000>; reg = <0xacb6000 0x4000>, reg-cam-base = <0xb6000>; <0xac42000 0x5000>; reg-cam-base = <0xb6000 0x42000>; interrupt-names = "ife"; interrupt-names = "ife"; interrupts = <0 467 0>; interrupts = <0 467 0>; regulator-names = "camss", "ife1"; regulator-names = "camss", "ife1"; Loading @@ -103,11 +109,13 @@ <&clock_camcc CAM_CC_IFE_1_CLK>, <&clock_camcc CAM_CC_IFE_1_CLK>, <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; clock-rates = clock-rates = <400000000 0 0>, <558000000 0 0>, <558000000 0 0>, <637000000 0 0>, <637000000 0 0>, <847000000 0 0>, <847000000 0 0>, <950000000 0 0>; <950000000 0 0>; clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_clk_src"; src-clock-name = "ife_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; clock-names-option = "ife_dsp_clk"; clock-names-option = "ife_dsp_clk"; Loading Loading @@ -144,11 +152,13 @@ <&clock_camcc CAM_CC_IFE_1_CLK>, <&clock_camcc CAM_CC_IFE_1_CLK>, <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; clock-rates = clock-rates = <400000000 0 0 0 400000000 0 0>, <400000000 0 0 0 558000000 0 0>, <400000000 0 0 0 558000000 0 0>, <480000000 0 0 0 637000000 0 0>, <480000000 0 0 0 637000000 0 0>, <600000000 0 0 0 847000000 0 0>, <600000000 0 0 0 847000000 0 0>, <600000000 0 0 0 950000000 0 0>; <600000000 0 0 0 950000000 0 0>; clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_csid_clk_src"; src-clock-name = "ife_csid_clk_src"; clock-control-debugfs = "true"; clock-control-debugfs = "true"; status = "ok"; status = "ok"; Loading
drivers/media/platform/msm/camera/cam_core/cam_context.c +1 −0 Original line number Original line Diff line number Diff line Loading @@ -448,6 +448,7 @@ int cam_context_handle_start_dev(struct cam_context *ctx, } } mutex_lock(&ctx->ctx_mutex); mutex_lock(&ctx->ctx_mutex); ctx->last_flush_req = 0; if (ctx->state_machine[ctx->state].ioctl_ops.start_dev) if (ctx->state_machine[ctx->state].ioctl_ops.start_dev) rc = ctx->state_machine[ctx->state].ioctl_ops.start_dev( rc = ctx->state_machine[ctx->state].ioctl_ops.start_dev( ctx, cmd); ctx, cmd); Loading
drivers/media/platform/msm/camera/cam_core/cam_context.h +2 −0 Original line number Original line Diff line number Diff line Loading @@ -180,6 +180,7 @@ struct cam_ctx_ops { * @refcount: Context object refcount * @refcount: Context object refcount * @node: The main node to which this context belongs * @node: The main node to which this context belongs * @sync_mutex: mutex to sync with sync cb thread * @sync_mutex: mutex to sync with sync cb thread * @last_flush_req: Last request to flush * * */ */ struct cam_context { struct cam_context { Loading Loading @@ -215,6 +216,7 @@ struct cam_context { struct kref refcount; struct kref refcount; void *node; void *node; struct mutex sync_mutex; struct mutex sync_mutex; uint32_t last_flush_req; }; }; /** /** Loading