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Commit e5f586c7 authored by Andrey Grodzovsky's avatar Andrey Grodzovsky Committed by Alex Deucher
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drm/amdgpu: Add interrupt entries for CRTC_VERTICAL_INTERRUPT0. 



This used by DAL ISR logic for VBLANK handling.

Signed-off-by: default avatarAndrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e9d672b2

drivers/gpu/drm/amd/include/ivsrcid/ivsrcid_vislands30.h

+99 −0
Original line number Diff line number Diff line
@@ -63,6 +63,105 @@ 
#define VISLANDS30_IV_SRCID_D6_GRPH_PFLIP		            18	    // 0x12  	

#define VISLANDS30_IV_EXTID_D6_GRPH_PFLIP                    0



#define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0           19      // 0x13

#define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT0           7



#define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT1           19      // 0x13

#define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT1           8



#define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT2           19      // 0x13

#define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT2           9



#define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SYNC_LOSS          19      // 0x13

#define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SYNC_LOSS          10



#define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SYNC               19      // 0x13

#define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SYNC               11



#define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SIGNAL             19      // 0x13

#define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SIGNAL             12



#define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT0           20      // 0x14

#define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT0           7



#define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT1           20      // 0x14

#define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT1           8



#define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT2           20      // 0x14

#define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT2           9



#define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SYNC_LOSS          20      // 0x14

#define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SYNC_LOSS          10



#define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SYNC               20      // 0x14

#define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SYNC               11



#define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SIGNAL             20      // 0x14

#define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SIGNAL             12



#define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT0           21      // 0x15

#define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT0           7



#define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT1           21      // 0x15

#define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT1           8



#define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT2           21      // 0x15

#define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT2           9



#define VISLANDS30_IV_SRCID_D3_EXT_TIMING_SYNC_LOSS          21      // 0x15

#define VISLANDS30_IV_EXTID_D3_EXT_TIMING_SYNC_LOSS          10



#define VISLANDS30_IV_SRCID_D3_EXT_TIMING_SYNC               21      // 0x15

#define VISLANDS30_IV_EXTID_D3_EXT_TIMING_SYNC               11



#define VISLANDS30_IV_SRCID_D3_EXT_TIMING_SIGNAL             21      // 0x15

#define VISLANDS30_IV_EXTID_D3_EXT_TIMING_SIGNAL             12



#define VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT0           22      // 0x16

#define VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT0           7



#define VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT1           22      // 0x16

#define VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT1           8



#define VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT2           22      // 0x16

#define VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT2           9



#define VISLANDS30_IV_SRCID_D4_EXT_TIMING_SYNC_LOSS          22      // 0x16

#define VISLANDS30_IV_EXTID_D4_EXT_TIMING_SYNC_LOSS          10



#define VISLANDS30_IV_SRCID_D4_EXT_TIMING_SYNC               22      // 0x16

#define VISLANDS30_IV_EXTID_D4_EXT_TIMING_SYNC               11



#define VISLANDS30_IV_SRCID_D4_EXT_TIMING_SIGNAL             22      // 0x16

#define VISLANDS30_IV_EXTID_D4_EXT_TIMING_SIGNAL             12



#define VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT0           23      // 0x17

#define VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT0           7



#define VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT1           23      // 0x17

#define VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT1           8



#define VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT2           23      // 0x17

#define VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT2           9



#define VISLANDS30_IV_SRCID_D5_EXT_TIMING_SYNC_LOSS          23      // 0x17

#define VISLANDS30_IV_EXTID_D5_EXT_TIMING_SYNC_LOSS          10



#define VISLANDS30_IV_SRCID_D5_EXT_TIMING_SYNC               23      // 0x17

#define VISLANDS30_IV_EXTID_D5_EXT_TIMING_SYNC               11



#define VISLANDS30_IV_SRCID_D5_EXT_TIMING_SIGNAL             23      // 0x17

#define VISLANDS30_IV_EXTID_D5_EXT_TIMING_SIGNAL             12



#define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0           24      // 0x18

#define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT0           7



#define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT1           24      // 0x18

#define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT1           8



#define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT2           24      // 0x18

#define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT2           9



#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A		            42	    // 0x2a	

#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A                 0