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Commit e53f101b authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "Merge android-4.14-q.151 (93b27559) into msm-4.14"

parents ea0ee416 0f3b8ff6

Documentation/admin-guide/kernel-parameters.txt

+9 −7
Original line number Diff line number Diff line
@@ -2402,8 +2402,8 @@ 
			http://repo.or.cz/w/linux-2.6/mini2440.git



	mitigations=

			[X86,PPC,S390] Control optional mitigations for CPU

			vulnerabilities.  This is a set of curated,

			[X86,PPC,S390,ARM64] Control optional mitigations for

			CPU vulnerabilities.  This is a set of curated,

			arch-independent options, each of which is an

			aggregation of existing arch-specific options.
@@ -2412,12 +2412,14 @@ 
				improves system performance, but it may also

				expose users to several CPU vulnerabilities.

				Equivalent to: nopti [X86,PPC]

					       kpti=0 [ARM64]

					       nospectre_v1 [PPC]

					       nobp=0 [S390]

					       nospectre_v1 [X86]

					       nospectre_v2 [X86,PPC,S390]

					       nospectre_v2 [X86,PPC,S390,ARM64]

					       spectre_v2_user=off [X86]

					       spec_store_bypass_disable=off [X86,PPC]

					       ssbd=force-off [ARM64]

					       l1tf=off [X86]

					       mds=off [X86]
@@ -2758,10 +2760,10 @@ 
			(bounds check bypass). With this option data leaks

			are possible in the system.



	nospectre_v2	[X86,PPC_FSL_BOOK3E] Disable all mitigations for the Spectre variant 2

			(indirect branch prediction) vulnerability. System may

			allow data leaks with this option, which is equivalent

			to spectre_v2=off.

	nospectre_v2	[X86,PPC_FSL_BOOK3E,ARM64] Disable all mitigations for

			the Spectre variant 2 (indirect branch prediction)

			vulnerability. System may allow data leaks with this

			option.



	nospec_store_bypass_disable

			[HW] Disable all mitigations for the Speculative Store Bypass vulnerability

Documentation/arm64/cpu-feature-registers.txt

+14 −3
Original line number Diff line number Diff line
@@ -111,6 +111,9 @@ infrastructure: 
     | Name                         |  bits   | visible |

     |--------------------------------------------------|

     | RES0                         | [63-48] |    n    |

     | TS                           | [55-52] |    y    |

     |--------------------------------------------------|

     | FHM                          | [51-48] |    y    |

     |--------------------------------------------------|

     | DP                           | [47-44] |    y    |

     |--------------------------------------------------|
@@ -133,8 +136,6 @@ infrastructure: 
     | SHA1                         | [11-8]  |    y    |

     |--------------------------------------------------|

     | AES                          | [7-4]   |    y    |

     |--------------------------------------------------|

     | RES0                         | [3-0]   |    n    |

     x--------------------------------------------------x
@@ -142,7 +143,9 @@ infrastructure: 
     x--------------------------------------------------x

     | Name                         |  bits   | visible |

     |--------------------------------------------------|

     | RES0                         | [63-28] |    n    |

     | DIT                          | [51-48] |    y    |

     |--------------------------------------------------|

     | SVE                          | [35-32] |    y    |

     |--------------------------------------------------|

     | GIC                          | [27-24] |    n    |

     |--------------------------------------------------|
@@ -193,6 +196,14 @@ infrastructure: 
     | DPB                          | [3-0]   |    y    |

     x--------------------------------------------------x



  5) ID_AA64MMFR2_EL1 - Memory model feature register 2



     x--------------------------------------------------x

     | Name                         |  bits   | visible |

     |--------------------------------------------------|

     | AT                           | [35-32] |    y    |

     x--------------------------------------------------x



Appendix I: Example

---------------------------

Makefile

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

VERSION = 4

PATCHLEVEL = 14

SUBLEVEL = 150

SUBLEVEL = 151

EXTRAVERSION =

NAME = Petit Gorille

arch/arm/boot/dts/am4372.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -1118,6 +1118,8 @@ 
				ti,hwmods = "dss_dispc";

				clocks = <&disp_clk>;

				clock-names = "fck";



				max-memory-bandwidth = <230000000>;

			};



			rfbi: rfbi@4832a800 {

arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c

+2 −1
Original line number Diff line number Diff line
@@ -966,7 +966,8 @@ static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = { 
	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),

	.sysc_flags	= SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |

			  SYSC_HAS_RESET_STATUS,

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |

			  SIDLE_SMART_WKUP),

	.sysc_fields	= &omap_hwmod_sysc_type2,